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    1,028 hyperlynx xilinx ddr2 tugasan ditemui, harga dalam USD
    Embedded Linux Development 1 hari left
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    I need to build embedded linux images for different development boards ranging from STM32 to Xilinx. Each image needs to have different modules configured in them (e.g ssh, ftp,, wifi, ethernet, etc.) Each board might have to be configured to boot from NAND/SD-card/TFTP depending upon the requirements. The UBOOT may need to be configured for various different features. The device tree might need t...

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    Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.

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    Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

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    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

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    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

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    Skillset Requirements : - Work with Hardware and Design Engineer to define the Board Design Architecture, system requirements, component selections and implementation. - Accountable for developing FPGA designs, board bringup, retrospective, continuous improvements and documentation at system level. - Work on RTL coding using Verilog, performing simulations using ModelSim or QuestaSim, proficient i...

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    I have a data stream of 24 Mega Bytes per second from custom Vivado IP core to processor on ultra96-v2 board. Custom core is connected to VDMA Xilinx IP. I need to write this data to SD card continuously. For data storage I use second SD card in USB card reader. I need an application and guide to setup it on my system.

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    main project is something with xilinx and matlab for the selection and sorting out send me a following as trail [log masuk untuk melihat URL] and verification of a third order IIR High Pass Filter with a cutoff freq of 5 KHz Using Xilinx System Generator Ref: [log masuk untuk melihat URL]

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    need to build a basic football game on FPGA and Xilinx. left side of the screen will be goal of one of the player and right side the other. Need to set 2 button. One of them for one player and one of them for other. In the middle there will be number 1 and it goes left and then to right. When it goes to left and player press the button, that number 1 will go right side. Therefore, players will be ...

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    This project needs Xilinx for coding for hardware modeling and design and implementation of 4 bit ALU. It needs to be done in next 24 hours. Please inbox me further details.

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    We are looking for a senior FPGA developer who has great experience with FPGA. If you can find LVDS/DSI IP Core license, it would be great for us. We will provide detailed documentation to shortlist candidates. Please feel free to contact us.

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    I need someone for a small project related with VHDL and counters experience with Xilinx will be apricated. is a very easy project so i think will not take much time also may be asked for an extra hour to explain the code (will be paid)

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    I have a few Xilinx Alveo U250 FPGA boards that need to be benchmarked for performance before investing in more boards. Scenarios will include data processing with TensorFlow and cryptocurrency mining capabilities and benchmarks. The developer should be comfortable with Xilinx Vivado, Linux and C++. Any experience with TensorFlow and cyrptocurrency miners like ethminer and/or cpuminer are a bonus

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    I have a ASIC SHA256 BTC miner project that was started and is about 80% to 90% complete. The main control board was done with Xilinx chip and the hash boards use ASICs Current Work that needs to be DONE: 1. Check of all PCB to make sure correct? Was notified from manufacture that there is traces that go nowhere [log masuk untuk melihat URL] the Xilinx firmware to work with the ASIC chi...

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    Hi, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

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    hello there excuse my ignorance but what would be the possibility of running a trading bot via a Xilinx card, kind regards

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    I need a working code in Verilog that is able to successfully simulate, synthesize and generate bitstream on Xilinx Vivado for FPGA. The code should be able to implement a Convolutional Neural Network and take as input weights and biases from a pretrained model in Python and then use them to identify the 28x28 pixel test image from a MNIST database. Whatever digit is identified by the code, releva...

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    functional block in xilinx 14.7

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    The task is to improve the existing kernel module or develop its minimal implementation. The kernel module is designed to control PCIe device, Xilinx FPGA board (FPGA code is already developed). FPGA board have 4 digital GPIO's configured as inputs and generate an interrupt on the PCIe bus - MSI interrupt with number 0-3, each number corresponds to one exact GPIO pin. The kernel module must r...

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    Hi Mykyta M. I noticed your profile and would like to offer you a role. I'm doing some xilinx work and need help with assembly work and schematics. 3 questions in total.

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    Hi Mairaj Ali, I noticed your profile and would like to offer you a role. I'm doing some xilinx work and need help with assembly work and schematics. 3 questions in total.

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    I am looking for someone who can design FPGA mining bitstreams . I'm looking for someone who can work with me long term . This is a very serious project. Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest prio...

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    I have a ASIC SHA256 BTC miner project that was started and is about 80% to 90% complete. The main control board was done with Xilinx chip and the hash boards use ASICs Current Work that needs to be DONE: 1. Check of all PCB to make sure correct? Was notified from manufacture that there is traces that go nowhere 2. Complete Xilinx firmware to work with the ASIC chips. Data sheet is available fo...

    $2874 (Avg Bid)
    Perjanjian Kerahsiaan
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    11 bida

    Hi, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7.

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    6 bida

    Project on VHDL using Xilinx Vivado. Need some one expertise on Digital Design using Xilinx Vivado.

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    I am looking for contractor to convert an project based on RISC-V currently running on Xilinx VC-707 utilizing Buildroot to YOCTO

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    The system will take in real time images and perform lane detection by running the software on an ARM processor implemented on a Xilinx Zync device. This system will enable future investigations into hardware acceleration of critical components such as the Canny detector in FPGA hardware. The system will be demonstrated on a Xilinx PYNQ [3] APSOC platform. This is the reason for the specification...

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    Hi, I need help with VHDL on Ubuntu Virtual Machine. I have a coursework that is due on Friday 30th April that I have been doing wrong and need assistance in completing it on time. It is about Mandelbrot and Julia sets. Knowledge on FPGA would be helpful. I have completed coding on Xilinx for windows and am struggling to incorporate it into Ubuntu and the templates provided. An expert in Ubuntu wo...

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    We are seeking an experience openstack developer to assist in building, modifying, and operating our existing accelerated cloud platform. The job will entail creating and managing multiple openstack clusters, modifying openstack services to enable advanced features, and planning future cloud architectures. Applicant must be willing to work on-site at least half-time Housing and relocation assist...

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    have been struggling with this lab for a long time, very hard for me, need assistance, related file is provided

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    Segera
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    i want long term employee. need to prepare report also. if you are expert in verilog, vhdl. please bid here

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    i want long term employee. if you are expert in verilog, vhdl. please bid here

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    i want long term employee. if you are expert in verilog, vhdl. please bid here

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    The topic is about combinational circuit, U should use Xilinx ISE simulation software, U have a specific time to finish and provide me with a) finding the prime implicants b) gates realization c) MUX2 Realization d) Schematic assembly e) Simulation And at the end , provide me with the whole report. My budget is 30$

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    I need a FPGA programmer to build a mining solution (Bitstream, driver, whatever is necessary) for mining Ethereum with a Xilinx U200 Card. The programmer should be able to develop everything what is necessary to run an ethereum miner on the following architecture: ASUS : Z10PE-D16-WS DDR 4 256GB Intel Xeon E5 2699 v4 Xilinx Alveo u200 SDAccl / Vitis / Vivado Ubunto as OS Please apply only...

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    I want to use the Xilinx DPU with an analog camera. This camera use PAL or NTSC encoding. For converting this video signal to digital, I bought the ADV7180 which output is in BT.656 YCrCb 4:2:2 format. So I would like to have this video streaming available in a /dev/video* to feed the DPU with it. I have found in github some BT656 decoders ip core which work well. I think I have an idea of what a...

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    I have an idea for a board that plugs into the PCIe slot of a computer and reads the memory directly and can also write to memory, basically a development board a Xilinx 7 series FPGA chip on it, the board will also need a (jtag) to upload instructions and will need a USB interface for communication. for reference I would like something similar to this product here. [log masuk untuk melihat URL]...

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    I am looking for somebody who can design me a schematic for a circuit I need. the idea I had was a device that plugs into the PCIe slot of a motherboard and can read/write directly to the memory of a computer like a DMA device, something similar to this product would be perfect [log masuk untuk melihat URL], I need someone to design the schematic so that I can put it onto a PCB, the device will ...

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    Need verilog Code and screenshot of output of the given question. Write and Synthesize the code in FPGA and ASIC designs separately and take screenshots of all simulations, schematics and clock/wave diagrams. Put sufficient comments in the code for ease of readability. We are flexible with the use of software but ModelSim or Xilinx is preferable. i want the project before 21 st of march 2021

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    I need help programming the Z-turn Board module (Xilinx Zynq-7020) with the VIVADO software tool. This is supposed to be on the FPGA: 1 x SPI (enhanced) for ADC 5 x SPI for DAC 7 x IIR filter (2 rows) sin / cos generator with variable phase sin generator arbitrary wave generator (1MS / s) 6 x adder 4 x multiplier approx. 70 variables All filters and most variables will be configurable from the h...

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    I have an earlier version of Xilinx FPGA project with SP6 in ISE and now it is required to rebuild this project on SP7 chip in Vivado, import is already done, but there are some error messages regarding IP etc. I am looking for help in completing the import and compile/build the project in Vivado.

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    Matlab code is written by Xilinx system generator software to realize defocus estimation of single image. The Gaussian function blur in the traditional monocular defocus image restoration process is replaced by Gaussian Cauchy mixture blur. The MATLAB and python codes of traditional defocus estimation methods can be provided for similar papers (the results of vivado HLS). We only need to write a f...

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    Ditampilkan Dimeterai Perjanjian Kerahsiaan

    To build and test, using Modelsim/ISE Simulator (ISim), a VHDL model of a Direct Digital Synthesiser (DDS) circuit which can them be implement on an FPGA board by using the Xilinx ISE 14.7 software tools to map the design onto the Xilinx Spartan-6 NEXYS-3 development board.

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    Hi, I have a board very similar to Ultra96v2. I have a very simple project (with a bare metal application) which works well in Ultra96v2 but it fails in my board. This project just show a color pattern (VTPG) through the DisplayPort. I suspect the failing reason may be related with the to DPPSU driver. I would like to run this sample project on my board and I need some help to debug and fix th...

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    Need to develop a simulink model

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    We are embarking on embedded software development using Vivado and Vitis Development tool for Xilinx evaluation board. The resource should be experienced with embedded software development Familiar with Armv7 / Armv8 architecture Familiar with Xilinx development tools like Vivado (IDE), Vitis unified software platform, compilers, debuggers and operating system The project is for establis...

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    Есть карта U200 Xilinx , ее реально задействовать в майнинге Ethash?

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    I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

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    Design a GCD for two 4-bit numbers (in your lecture notes, we have already done this). It will output the binary value of the greatest common divisor of those two 4-bit numbers.

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