Tapis

Carian terbaru saya
Tapis melalui:
Bajet
hingga
hingga
hingga
Kemahiran
Bahasa
    Status Pekerjaan
    1,361 verilog projects tugasan ditemui, harga dalam USD

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $21 / hr (Avg Bid)
    $21 / hr Avg Bida
    5 bida

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    $154 (Avg Bid)
    $154 Avg Bida
    4 bida

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    $4470 (Avg Bid)
    $4470 Avg Bida
    24 bida

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $390 (Avg Bid)
    $390 Avg Bida
    3 bida

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    $65 (Avg Bid)
    $65 Avg Bida
    18 bida

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Avg Bida
    16 bida

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
    $23 Avg Bida
    18 bida

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    $46 (Avg Bid)
    $46 Avg Bida
    16 bida

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
    $23 Avg Bida
    21 bida

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
    $22 Avg Bida
    17 bida

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
    $21 / hr Avg Bida
    20 bida

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
    $131 Avg Bida
    19 bida

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
    $122 Avg Bida
    13 bida

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1988 (Avg Bid)
    $1988 Avg Bida
    5 bida

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
    $100 Avg Bida
    8 bida

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $122 (Avg Bid)
    $122 Avg Bida
    19 bida

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
    $184 Avg Bida
    15 bida

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
    $86 Avg Bida
    5 bida

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
    $106 Avg Bida
    11 bida

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
    $132 Avg Bida
    7 bida