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    2,540 vhdl project tugasan ditemui, harga dalam USD

    Super easy project. I just need to change the HEX display for a seven segment decoder. I will send you a zip file with all of the information. Please message me for details.

    $26 (Avg Bid)
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    6 bida

    Using ISE design suite. Design an 8-Bit ALU (x and y are inputs and Result is output), based on modular arithmetic and logic circuits and 8x1 line multiplexer, in VHDL. Add comments to your code whenever required. Design a test bench to verify your designed circuit functionality. Add simulation results screen shot. ** I will share more details if you will do it

    $50 (Avg Bid)
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    3 bida

    Implement your design using Magic VLSI layout tool to generate your project layout Test your design using irsim to simulate your project. Reqired Magic VLSI tool is running on ubuntu OS SRAM PROJECT VLSI

    $103 (Avg Bid)
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    3 bida

    I want to read and write 180 values in B-RAM , VIVADO using VHDL coding ,Will provide reference code

    $17 (Avg Bid)
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    1 bida

    I need help with my project. You must be good at RISC-V and Verilog. The project is related to Cache. Please check the file

    $30 (Avg Bid)
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    1 bida

    i need help in Implement MIPS processor pipeline and instruction and data caches, using VHDL. i will provide more details in the chat.

    $50 - $51
    $50 - $51
    0 bida

    hi everyone, I need a fractal image compression code (for a 128*128 image) implemented on a DE2 cyclone II in the M4K memory which has 105 blocks.

    $143 (Avg Bid)
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    3 bida

    project consists in a virtual analog music synthesizer running on Myr z-turn board, i need a developer for finishing this project and future ones.

    $34 / hr (Avg Bid)
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    8 bida
    Verilog/VHDL 4 hari left
    DISAHKAN

    I need a person who can do verilog

    $20 / hr (Avg Bid)
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    5 bida
    FPGA4student 4 hari left
    DISAHKAN

    This VHDL project is to design and implement noise filtering, metastabiliy and synchronization of given signals

    $255 (Avg Bid)
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    4 bida

    I want program code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite) and I hope all of these including in the report also simulation in one report

    $57 (Avg Bid)
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    6 bida
    vhdl encoder 4 hari left
    DISAHKAN

    I am looking for a real-time A-law/U-law encoder written in VHDL for implementing in a Lattice XP2 FPGA. The input to the encoder will be 16 bit PCM16, the output will be 8 bit a-law/U-law. The PCM16input will comprise of 24 channels. The CODEC will have 1 16 bit input. The 2k channels will be fed into the codec sequentially in blocks of 32 16bit samples. The CODEC shall handle a total of 10 Megasamples/second in real time. Each block of 32 16bit PCM data will be accompanied with a 4 bit channel number 0-23. The 8 bit companded output should have an extra 4 bit output that will hold the channel address that corresponds to the PCM channels from which it was created. The target FGA is a Lattice XP2-8 but the code will be demonstrated in the Lattice XP5 eval board as attached.

    $2125 (Avg Bid)
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    2 bida
    Quartus II / VHDL Coding 3 hari left
    DISAHKAN

    I am looking for an expert to do coding in VHDL language and then do simulation in Quartus II. I will share work details in chat

    $147 (Avg Bid)
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    3 bida

    looking support for the verilog program and MIPS urgently . this tasks to be tested in vivado software . here i am attaching the detailed information for the tasks to be done and the supporting binaries which requires for the codes

    $64 (Avg Bid)
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    3 bida

    I want a code for 12/24 hr clock implementation in VHDLon basys 3 board

    $27 (Avg Bid)
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    5 bida

    I have some tasks related to computer architecture. I want someone who is an expert in VHDL.

    $10 / hr (Avg Bid)
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    2 bida

    I have some tasks related to computer architecture. I want someone who is an expert in VHDL.

    $3 / hr (Avg Bid)
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    1 bida

    I want to convert VHDL code to VERILOG code.

    $33 (Avg Bid)
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    I need this mini project in VHDL with all displayed on display. YouTube link is there for calculator help to understand. According to that program it.

    $127 (Avg Bid)
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    3 bida

    Assalam o alaikum !!! I am hiring electrical engineers for working on my projects in following areas of electrical & electronics engineering: 1) FPGA (VHDL/Verilog) 2) Matlab 3) Multisim I have a lot of work in all the fields mentioned above. Its a big opportunity to work with us for long term basis. Even if you are a new freelancer, feel free to place your bid. I AM HIRING EXPERTS FROM PAKISTAN ONLY

    $96 (Avg Bid)
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    11 bida

    Multiplication and addition of two 16 bit numbers with various resource constraints. Below is the expression : Y= x0h0+x1h1+x2h2.........x0h9. You should perform the above in a specific manner in VHDL code . For more detail find the attached file.

    $131 (Avg Bid)
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    3 bida

    Two 16-bit number from X0 and X9 and H0 to H9 multiply them and add them . Code shall be done in VHDL Y= x0h0+x1h1+x2h2+x3h3+........x9h9. For more details find the attached Set of Question.

    $112 (Avg Bid)
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    4 bida

    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit (DE10-Lite) and I need report about a project

    $37 (Avg Bid)
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    5 bida

    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

    $32 (Avg Bid)
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    5 bida
    FPGA Project Tamat left

    1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. Optical Data link 5 Networking concepts

    $406 (Avg Bid)
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    11 bida
    VHDL Module Tamat left

    Project of building a VHDL program for a simplified version of image equalization. The project specifics will be handed out to you as soon as we agree on the job.

    $181 (Avg Bid)
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    4 bida

    I need an image equalizer written in VHDL language. The semplified algorithm to use should be: DELTA_VALUE = MAX_PIXEL_VALUE – MIN_PIXEL_VALUE SHIFT_LEVEL = (8 – FLOOR(LOG2(DELTA_VALUE +1))) TEMP_PIXEL = (CURRENT_PIXEL_VALUE - MIN_PIXEL_VALUE) << SHIFT_LEVEL NEW_PIXEL_VALUE = MIN( 255 , TEMP_PIXEL) In this project the program recieve the image dimension in 2 bytes, the first one is for columns and the second one is for rows. The third byte is the first byte of the image that the program recieves in input. Extra Notes: 1. FLOOR(LOG2(DELTA_VALUE +1)) is an integer number 2. The project should be able to process more than one image, but the input image will never change during the execution, only when the DONE signal is high 3. The module will start ...

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    7 bida

    I have uploaded the file in which all the details available .

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    5 bida

    I need someone who can develop a current small project written in VHDL. It should be a game dispaying on vga monitor.

    $73 (Avg Bid)
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    6 bida

    Multiplication and addition of two 16 bit numbers with various resource constraints. Below is the expression : Y= x0h0+x1h1+x2h2.........x0h9. You should perform the above in a specific manner in VHDL code . For more detail find the attached file.

    $102 (Avg Bid)
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    8 bida

    4-stage pipelined design in a structural/RTL manner with several modules operating simultaneously. Each module represents a pipelined stage with its interstage register

    $193 (Avg Bid)
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    3 bida

    I want a cars parking , counter that displays the number of cars on 7segment starting from zero to 99

    $17 (Avg Bid)
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    4 bida
    VLSI Design Tamat left

    VHDL code ,ModelSim to simulate the D flip-flop , NP Domino 8-input AND circuit

    $3 / hr (Avg Bid)
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    8 bida

    Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.

    $30 (Avg Bid)
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    6 bida

    Car parking system counting from 0 to 99 in 7 segment using vhdl , fpga I have the code and testbensh but I have a problem when I click on the push buttons the 7 segment does not show the numbers Model of fpga kit=> (( rz easyfpga a2.2 ))

    $24 (Avg Bid)
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    10 bida

    Need an expert in VHDL and System Verilog

    $177 (Avg Bid)
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    9 bida

    I have a project on implementing a 32-bit processor in VHDL or Verilog

    $67 (Avg Bid)
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    11 bida

    Design Problem specification: To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board.

    $22 - $180
    Dimeterai
    $22 - $180
    3 bida

    I am looking for expert in VHDL/Quartus from Pakistan, I will share work details in chat

    $30 - $250
    Dimeterai
    $30 - $250
    3 bida

    I developed a system that consists of 2 camera and 1 ethernet. The FPGA will get the image sensor data from 2 cameras and will process algorithm on the images. After processing, FPGA will send streaming data and processed data to the computer via Ethernet port. The protocol will be based on TCP/IP. I am looking for a long-term partner. I have many projects, so this will lead to other opportunities.

    $611 (Avg Bid)
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    9 bida

    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

    $15 (Avg Bid)
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    ...module. It's very easy that your code is un-synthesizable, if you are not familiar with verilog. If you synthesize everything together only at the end, and your code is not synthesizable. It's very possible that you need to re-write your code from scratch. Tutorial - Verilog You have to design several modules using Verilog, so you need to learn how to use this language. Many of you may have learned VHDL (another hardware description language) in the logic design course; you will find that Verilog is much simpler. Since Verilog is based on C, you will find it quite natural if you are familiar with C. Course material covering Verilog can be a good reference to initiate you. Here is a very good reference book on Verilog, Verilog HDL : a guide to digital design and synthes...

    $535 (Avg Bid)
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    5 bida

    I have some tasks related to HDMI and VGA display. I want someone who is an expert in VHDL.

    $94 (Avg Bid)
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    4 bida

    I have some tasks related to HDMI and VGA display. I want someone who is an expert in VHDL.

    $14 (Avg Bid)
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    1 bida

    I have some tasks related to HDMI and VGA display. I want someone who is an expert in VHDL.

    $32 (Avg Bid)
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    2 bida

    I need help to implement a display controller using verilog/VHDL. I will share specfic details to the choosen freelancers.

    $14 (Avg Bid)
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    2 bida

    I need help to implement a display controller using verilog/VHDL. I will share specfic details to the choosen freelancers.

    $50 / hr (Avg Bid)
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    1 bida

    In this lab exercise, you will pipeline the Small16 microprocesso...worry about any data forwarding or hazard mitigation techniques. You will need to modify your lab 3 VHDL code, including your datapath, control, and processor; for the control, I recommend making separate control combinational logic for each stage of the pipeline. You may also want to modify and increase the duration of the simulation; you can do this by increasing how many clock cycles are simulated within the stimulus process. Refer to Canvas for additional VHDL source files which will be needed in your pipelined design. Remove VHDL source files (from lab 3) which are not necessary for your pipelined design. Use the instruction code found in the new instruction memory VHDL source file to test...

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    I need help to Modify VHDL for alarm clock. i will share more information in chat.

    $55 (Avg Bid)
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    5 bida