Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.
Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [log masuk untuk melihat URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 thr...
I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job
We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx
I have the scheme of the project need only to work with the basys 3. Only to use buttons and switches from the basys3. Need the whole code in VHDL for Vivado.
Develop a 32‐bit single or multi‐cycle CPU capable of performing a search for prime numbers. CPU
I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is [log masuk untuk melihat URL] picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neuron with
Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from an electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relationship with the perfect electrical engineering freelancer. Thanks.
Hello, I'm currently working on a project that I am struggling with due to lack of VHDL experience. Want to create an SPI driver and interface it with a Microblaze softcore processor and the on-board accelerometer (ADXL362) so that the processor can read the accelerometer data.
I have some simple VHDL tasks. My deadline is tomorrow. 1. Suggest a structural and behavioral description of a bidirectional cyclic shift register. 2. Suggest a structural and behavioral description of a bidirectional arithmetic shift register. Use parallel generation operators and configuration options. 3. Create a subroutine that performs the conversion
Implementation of FOPID controller based FPGA using VHDL.
Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relation with the perfect electrical engineering freelancer. I need to hire 3 freelancers for 3 copies of the task. Thanks
I have the Deo Nano Soc and I want to read data using DMA. I need to read at a rate of about 2MB/s. I have used VHDL for a while and if you could provide some protocol/instructions at the top level, I could do the rest.
Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have
...area. I have been fighting with Quartus for a while. I can do everything else on this project. I would provide the c-code so you could see how it writes a string of words to the RAM. I also have some VHDL code if you like that is about 98% there. A person skilled in VHDL and using Quartus should be able to write the code from scratch in about an hour or
I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.
Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relation with the perfect electrical engineering freelancer. Thanks.
I want an MP3 player built on FPGA board based on VHDL language. I want a seasoned hands on FPGAs who can build me this by Apr 2nd, 2019. The FPGA board I have is Xilinx Spartan-6 LX45 (Atlys circuit board) specifically on which it will have to be built and synthesized. I have uploaded an image of the board and feel free to ask me for any information
Hello Freelaners! My project is simple and should be implemented on VHDL by 31 March. I would like you to use the program Vivado of xilinx, as this is the one I am using and could test. I ATTACH the description so kindly review and let me know if interested so we could talk about further details and begin if we agree. Happy Biding :)
The brightness measurement with help of PMODALS sensor (https://s...-100%)and ADC value (0-255). You can see block schematic. Whole design needs to be in VHDL and C(for mc8051) code and tested with Model Sim IntelFPGA. Test bench in Model Sim included. Synthesis is in Vivado. Keywords: Basys3, FPGA, Ambient light sensor, SPI, mc8051, VHDL, C, Vivado
...offer you my project. I have a small task which is creating float-point format (type) with specific precision and certain bitness of exponent and mantissa using C ? For example, 40-bit float-point number with 10-bit exponent and 30-bit mantissa. I Think you will need to use some kind of libraries like MFPR. I will test the data using VHDL design with
Implement a UDP communication protocol in VHDL to transmit and receive UDP packets. A linux based PC will send a UDP packet of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard. Important
Need to develop a very simple game using VHDL, to be run on an Altera DE1-SoC FPGA board. The game will use as external 4x4 keypad which will be connected to the board via one of the GPIO ports on the board. Also the game will use some 7-segment displays on the board to display some information regarding the game. The game itself is quite simple and