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    2,425 xilinx fpga project tugasan ditemui, harga dalam USD

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

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    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

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    customization of an SDR 3 hari left
    DISAHKAN

    We are looking at scanning,capturing and decoding multiple cellular frequencies(European 2G/3G/4G(LTE) bands) with an SDR. Currently using a simple rtl-sdr for this case but seeing as it lacks the frequency range(max 1800mhz) and has very little bandwidth(2.4MHz) we would like to upgrade to a better SDR. The goal is to analyze multiple simultaneous communication channels in real time. We are loo...

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    Build a CNN 3 hari left

    Hi, I need : * CNN IN FPGA using my mac unit? *Verilog *MNIST DB

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    PCB Design 1 hari left

    Use the xtal oscillator board that I designed and that works together with the FPGA to read the GPS data and then synchronise the 40 MHZ Voltage controlled Xtal oscillator to the 1 second pulse produced by the GPS. I will provide more details on chat.

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    se trata de hacer unas practicas en la placa KCU105 de Xilinx utilizando el modulo AD9361 en simulink para exportar a código HDL para implementar en físico el sistema operativo de Windows

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    FPGA expert needed 1 hari left
    DISAHKAN

    I am looking for an expert in FPGA, its not a simple task, only expert place bids. will share details in chat

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    Need someone who has the PLDa PCIe ipcore license for Xilinx Vivado to help compile a FPGA project. I'll give you the source code. You compile and give me the bit file and compiled project.

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    The test program used for transmited data between DDR4 of FPGA and DDR4 of PC adopted windows 10 or win7 system via PCIe 3.0 x8. A tested result shows that the speed of PCIE3.0 *8 is over 7GB/s , which is tested by xilinx Kcu1500 FPGA board. However, the speed under win7 / win10 is only about 4.5-4.9GB/s. The minimum speed threshold should be 5.5 GB/s. And it will be helpful if the speed...

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    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    i have projects related to all of these micro-controllers: Raspberry Pi FPGA PIC microcontroller STM microcontroller so looking for experts who can assist me with these projects

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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

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    I want to make this tool by updating the hardware to a new fpga board, here is source code and some documents about it. [log masuk untuk melihat URL]:projects:smartlogic [log masuk untuk melihat URL] [log masuk untuk melihat URL]

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    More details will be shared via chat

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    More details will be shared via chat

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

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    PANEL = Artix-7 100t - ERROR: [Labtools 27-2269] Hi, I am facing ERROR: [Labtools 27-2269] after issueing the open_hw_target command. Vivado 2019.1 Windows 10 Connected through micro USB for serial communication. MODE = JTAG Any suggestion as to how can i detect the devide to burn my bitstream for execution? Thanks!!

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    I need transmit data from DDR of Xilinx Kintex-7 to PC (windows 10 system). I would like to use PCIe 3.0 x8 to realize the project, But I found that the speed is not enough if I use the drive source code ordered by xilinx, which is only about 4.5-4.9GB/s. The minimum speed threshold should be 5GB/s. And I expect the speed is more that 6GB/s. Demands: 1) windows 10 system. 2) the speed is not l...

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    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

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    Using LabVIEW, FPGA & RT softwares, I need a data logger with cRIO-9047 chases for following modules. 1) 9205 2)9237 3)9232 4)9361 5)9467 I want to log data in RT (FPGA) at 10Khz for no more than 3 minutes. Two Load Cells, One Accelerometer, linear displacement through encoder, Trigger input by some switch, Speed tracking. After recording data I want to analyse it specially Accelerometer dat...

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    i need a coder Tamat left

    FPGA Bode Designer for Real-time application

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    simple fpga addition subtraction code

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    simple fpga addition subtraction code

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    Have a design that is synthesizable and works properly on FPGA (nexys video - artix-7 based). The clock is set via clock wizard, and I need to make it flexible without the need to regenerate bistream every time. The dynamic clock setting can be done via "sw" pins (nexys video has 8 sw pins on board). When new clock frequency is set, the expectation that design will reset and restart oper...

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    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

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    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

    $204 (Avg Bid)
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    6 bida

    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

    $133 (Avg Bid)
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    8 bida

    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

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    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

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    I am looking for skilled programmer from Bosnia or Slovenia.

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    I need to run some program (FPGA miner) on aws, unfortunately the problem is, its not compatible with the latest fpga ami from aws Here is the miner and the tutorial [log masuk untuk melihat URL] its hdk source only can run on version 16.00 ami but its already being deleted by aws, and now the latest is version 18 ami (cmiiw) if somehow you can make it compatible again with version 18, i can p...

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    I need to implement a true random generator on zedboard fpga. noise source will be ECG signal.

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    Set up FPGA to mine Cryptonight v8. Consulation on which FPGA boards are best to buy.

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    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    Need Signal Processing and FPGA based algorithm implementation expert.

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    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

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    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

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    Hi, We are looking for fpga dev who can create working ethash algo/bitstream for fpga ( U250 board ) Timeline: a.s.a.p or as long as it takes Requirements: Senior experience working with fpga Questions: Shoot me a message Payment: Available after intensive testing and proof it actually works.

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    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

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    Build an FPGA Bitstream for Xilinx 420T PCI Card. Please contact for specific details.

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    This job is to create altium schematic and PCB library. Component part number is 10M50DAF256I7G. it is MAX10 FPGA [log masuk untuk melihat URL] budget is $20. please contact me if you interesting this project. Thanks.

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    We have developed Grostl RTL code for Grostl hash. We need an expert to optimize the code so I will use less LUT in Xilinx FPGA. We use Xilinx VCU9P and the goal of this project is to reduce the LUT down to 21%. The c code link is : [log masuk untuk melihat URL] The RTL code and spec. will be sent after the project is awarded. Target FPGA : Xilinx UltraScale+ XCVU9P Target utilization : 21% ...

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