DIN Enclosure ESP32 Module Development

Technical Specifications — ESP32 Module (8× DI 24 V + 2× AI 0–10 V / 16-bit) for DIN enclosure 1) Functional requirements * Board supply: 24 Vdc. * Digital Inputs (DI): 8 channels, 24 Vdc field level, using 2× TLP293-4 (4 channels each). Digital input reference GND is the board supply GND. * Analog Inputs (AI): 2 independent channels, 0–10 Vdc, read by ADS1115 (16-bit, I²C). * MCU: ESP32-WROOM-32E. * Programming: on-board male header for ESP32 UART/boot. * Reset control: a micro switch push button dedicated to reset/enable of the ESP32, externally accessible once assembled in the enclosure. 2) High-level electrical architecture * Convert 24 Vdc to the logic rails required by ESP32 and ADS1115. * 8× DI @ 24 V → TLP293-4 → logic side 3.3 V GPIOs on ESP32 (open-collector style on logic side). * 2× AI @ 0–10 V → input conditioning (ensure AIN within GND..VDD of ADS1115) → ADS1115 in single-ended mode. * I²C between ESP32 and ADS1115 at 3.3 V per datasheets. * Keep field (24 V) and logic (3.3 V) domains separated in routing and reference planes. 3) Power (guidelines) * Provide suitable input protection, filtering, and decoupling for the complete load. * Power LED at 3.3 V. * Grounding, planes, and distribution per good EMC/EMI practices. 4) Digital inputs — 8 channels (TLP293-4) * Use 2× TLP293-4 (package as per datasheet). * Field side: interface at 24 Vdc. * Logic side: phototransistor to ESP32 GPIO (3.3 V) with pull-ups on the logic side; define channel active level consistently across all inputs. * Separate field/logic routing and returns; common reference is the board GND. 5) Analog inputs — 2 channels (ADS1115, 0–10 V) * ADS1115 powered at 3.3 V. * Required input range: 0–10 Vdc per channel. * Conditioning: guarantee AIN stays within GND..VDD of the ADC; single-ended measurement. * Configure FSR/PGA and data rate in firmware as needed. 6) ESP32, programming, reset (micro switch push button) and mechanics * ESP32-WROOM-32E: follow official footprint and antenna keep-out (no copper/components). * Programming header 1×6 (2.54 mm): GND, 3V3, RX0, TX0, EN, IO0 (clear silkscreen; accessible without removing the PCB). * Micro switch push button for reset: acts on EN/RESET per ESP32 datasheet; must be externally accessible when mounted in the enclosure and identified on silkscreen. * DIN enclosure: the PCB must fit the Patola DIN-FUNDO-075; respect internal dimensions, fixing points, max height, and connector orientation. 7) Pinout (suggestion) * DI (8 ESP32 GPIOs): choose suitable digital GPIOs (e.g., 32, 33, 25, 26, 27, 14, 12, 13). * I²C: SDA = GPIO21, SCL = GPIO22. * ADS1115: AIN0 = AI1; AIN1 = AI2 (single-ended, 0–10 V conditioned). * UART0 (programming): TX0 = GPIO1, RX0 = GPIO3; EN and IO0 on the header. 8) Layout (general guidelines) * Physically separate field (24 V) and logic (3.3 V) areas; keep analog traces short and away from DI and switching lines. * Continuous GND planes on logic/ADC domain; place decoupling close to VDD pins. * Respect ESP32 antenna keep-out and Patola enclosure clearances. * Track widths, drills, and clearances per fabricator capability and isolation requirements. * Silkscreen: IN1..IN8, AI1/AI2 0–10 V, +24 V, GND, SDA/SCL, TX/RX, EN/IO0, RESET (push button). 9) Footprints and packages * ESP32-WROOM-32E: official footprint per datasheet. * ADS1115: package per datasheet (e.g., TSSOP-10). * TLP293-4: package per datasheet. * KRE KF128 3-way screw terminals: manufacturer’s nominal pitch; allow chaining as needed. * Header 1×6, 2.54 mm (male). * Micro switch push button: package compatible with enclosure height/opening; operable from outside. 10) BOM (Bill of Materials) At minimum include: Designator, Qty, Description, Manufacturer, MPN, Package/Case, Notes. Key items: ESP32-WROOM-32E, ADS1115, 2× TLP293-4, KRE KF128 terminals, 1×6 male header, micro switch push button for reset, power conversion parts, passives, LEDs, connectors, and enclosure-related mechanical items. 11) Manufacturing outputs * Gerbers, Excellon, stack-up (if applicable), Pick&Place (XY), BOM, PCB STEP 3D. 12) Acceptance criteria * Verified fit in Patola DIN-FUNDO-075; front access to terminals and external access to the reset micro switch push button. * DRC/ERC clean; nets and silkscreen consistent. * Complete BOM with correct MPNs and packages. * Programming via header operational; DI and AI (0–10 V) testable via TPs; reset via micro switch push button works as intended. Scope & Deliverables * Complete schematic (native CAD file + PDF). * Symbols/footprints libraries for all components used. * PCB layout ready for fabrication (DRC/ERC clean). * Manufacturing outputs: Gerbers, Excellon (drill), Pick&Place (XY), BOM (with MPN/manufacturer/package), and PCB STEP 3D. * Mechanical drawing (DXF/STEP) with outline, holes, and connector locations, compatible with the Patola enclosure. * Silkscreen with clear channel IDs, polarities, voltages, programming pins, and reset push button. * Basic test plan with labeled test points (power, I²C, DI, AI). References * Patola DIN-FUNDO-075: [login to view URL] * ESP32-WROOM-32E (datasheet): [login to view URL] * ADS1115 / ADS111x (datasheet): [login to view URL] * TLP293-4 (datasheet): [login to view URL] * Programming header (commercial reference): [login to view URL]

Project ID: 39743607