Design an MPEG-2 encoder IP Core in Verilog to compress a video signal resolution 640x480 and should have the performance to make video streaming. The input images will be in the RGB color space. The IP core arquitecture should be Pipeline. The output bitstream resulting should be compatible with a MPEG2 reproductor for testing.
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I have worked as FPGA engineer for 6 years and out of which I have worked in video and image processing domain for 5 years. I have expertise in verilog and VHDL both. I can complete this job with greater efficiency.