Tongue Segmentation Project - Rewrite or modify C code to make it synthesizable to simulate in HLS tools

This is the continuous work from a developer, which he has done the algorithms of tongue segmentation into c code. For our part, we need to use or re-write to make the c code synthesizable to be implemented on HLS design flow and generate into HDL and do the validation on the performances, area, speed.

Because from our understanding, the HLS compiler could run simulation, synthesis, export rtl and run the c/rtl-co-simulation and generate the HDL and RTL

To run the simulation on HLS compiler, it need a source code and testbench

But with the only high level synthesis c code, i don't know how to rewrite or modified to make it synthesizable to simulate in HLS tools

Kemahiran: Pengaturcaraan C, Kejuruteraan Perisian, x86/x64 Assembler, Verilog / VHDL, Kejuruteraan Elektrik

Tentang Klien:
( 22 ulasan ) Cheras, Malaysia

ID Projek: #30270465

6 pekerja bebas membida secara purata $163 untuk pekerjaan ini


Hello. I am digital design engineer with +5 years of experience in RTL design in Verilog/VHDL. I have experience in converting c/matlab code into a synthesiable hardware code. I have read your code and project descript Lagi

$250 USD dalam 7 hari
(96 Ulasan)
(2 Ulasan)

Hi, Im a FPGA desiner, I have experince in HLS VIVADO. I run your file in HLS , I found some problems related to the file handling. File handling function are not supported by HLS so we have to re-write the code. Pls Lagi

$140 USD dalam 7 hari
(11 Ulasan)

Greeting! I have done tongue segmentation project before but it was in python. If python is acceptable for you then I can share it with you. thanks Regards

$167 USD dalam 2 hari
(2 Ulasan)

Hi I have a good skill in C/C++, C#, JAVA programing. I have finished many projects using C/C++, C#, JAVA. I also know fundamental knowledge of Audio Processing. I can do it perfectly in your timeline. Let's discuss mo Lagi

$140 USD dalam 7 hari
(0 Ulasan)

I have 4 years of experiences high level synthesis and designing rtl projects for defence writing the test benches and verify the design timing constraints, knowledge in desing flow synthesis to generating but stream f Lagi

$140 USD dalam 7 hari
(0 Ulasan)