I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA
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Dear sir I have more than 10 years experience in digital design using vhdl and verilog please check my profile also please message me so that we can discuss
I have an experience in Verilog. So if it's need to be coded in Verilog and If interested please ping in chat box. I'll provide you the proper code for FIR filter and please provide the spec.
Design Engineer with Experience in Large Scale Systems Design with Practicing in Verilog, VHDL, SystemVerilog and Programming C, C++, Python. Let's Discuss Further.
I would like to complete this project for an FIR Filter to be implemented on an Altera FPGA. Which FPGA model does design need? At what frequency should the project work?