Floating-point Unit Development(Quartus Prime Verilog)

In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the 'NaN' cases.

For the project demonstration, interface the FPU to the DE-10 RAM and perform the operation A*B+C on 1000 data triplets (A, B, C). Transfer the results back to the RAM, then upload to the PC for display. Verify the results by comparing them with another method (e.g., C program, spreadsheet etc.). This project Must be built using Quartus Prime's Verilog code. A code example is attached, you can follow the example but please modify it to fit my project description.

Kemahiran: Pengaturcaraan C++, Kejuruteraan Elektrik, FPGA, Mikropengawal, Verilog / VHDL

Lihat lagi: quartus prime handbook volume 3, quartus prime pro handbook, quartus prime standard edition, quartus prime help, quartus floating point, quartus prime handbook volume 2, intel quartus prime pro edition handbook volume 2, quartus prime pro documentation, program floating point full adder verilog modelsim, floating point arithmetic adder project verilog, program floating point full adder using verilog modelsim, verilog code floating point addition, floating point verilog, floating point unit verilog, floating point addition verilog, single precision floating point verilog, floating point unit verilog code, verilog single precision floating point addition unit, floating point verilog code, verilog code single precision floating point addition

Tentang Majikan:
( 0 ulasan ) melbourne, Australia

ID Projek: #19729832

Dianugerahkan kepada:


Dear sir I have more than 10 years experience in digital design using Quartus, please message me so that we can discuss

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I have 10 years of experience in design and verification using Verilog. Please message me. Best regards.

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Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 5 years. I did similar projects as well. Please let me know if the requirement is still there I can do the work. Thanks

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