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I have scheduled a short VLSI module for a class of third-year engineering students and need it to start from the ground up. The training must touch on three pillars—Digital Design, Analog Design, and a high-level view of System-on-Chip flows—always keeping explanations at a beginner’s pace. The plan is to combine theory with practice: after introducing core concepts, each topic should segue into a hands-on lab that walks students through RTL-to-GDSII using at least one EDA tool (Cadence, Synopsys, or an open-source alternative such as OpenLane). Audience • 25 students with minimal semiconductor background • Expect interactive sessions and plenty of Q&A time Delivery • Live online lectures totalling roughly 8–10 hours • Recorded walkthroughs for tool demos • Printable lab sheets so students can work offline Deliverables • Detailed syllabus with learning objectives and tool-setup steps • Slide deck (PPT or PDF) for every lecture • Lab manuals containing Verilog/VHDL samples, schematic capture tasks, and a mini SoC integration project • Pre- and post-course quizzes with answer keys • Cloud links to all session recordings Acceptance criteria 1. Content reviewed by me 48 hours before each class. 2. Labs execute on our Linux machines without requiring paid licences. 3. At course end, students complete the mini project with no more than 20 % guidance on average. Please outline the toolchain you intend to use and, if available, attach a sample of previous VLSI training material so I can gauge your teaching style.
Project ID: 40465146
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4 freelancers are bidding on average ₹23,750 INR for this job

Why I Am Suitable for This Role Working experience as a Verification Engineer with exposure to SystemVerilog, UVM, RTL concepts, assertions, and SoC verification flows Strong understanding of digital design fundamentals, verification methodologies, and semiconductor workflows from RTL to verification/debug Experience conducting technical mentoring and online sessions, helping students understand concepts through practical examples rather than theory alone Able to simplify topics for beginners using: Visual explanations Incremental lab exercises Real industry-style examples Interactive Q&A sessions
₹25,000 INR in 7 days
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I have good knowledge on digital electronics and verilog and system verilog and uvm and protocols,i can handle i can explain breafly every topics and i teach them topology print etc
₹25,000 INR in 8 days
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I am Dharshini, an ASIC/SoC Design Verification Engineer trained at Maven Silicon, Bangalore. I have hands-on experience in Digital Design, Verilog, SystemVerilog and RTL-to-GDSII flow using Synopsys Design Compiler and SpyGlass Lint. I can deliver beginner-friendly VLSI training covering Digital Design, SoC fundamentals and hands-on EDA tool labs using open-source tools like OpenLane and QuestaSim. I will prepare detailed syllabus, slide decks, lab manuals with Verilog samples and pre/post quizzes. All labs will run on Linux without paid licences.
₹20,000 INR in 14 days
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I am very interested in delivering the VLSI Basics Training for your third-year students. I have strong practical experience in VLSI, having worked on RISC-V Processor Design, CNN Accelerator, and tape-out projects. This gives me clear understanding to explain concepts from beginner level. My Training Approach: Cover three pillars: Digital Design, Analog Design, and high-level SoC flow Every theory session followed by hands-on lab Use OpenLane (open-source) for full RTL-to-GDSII flow so students can run labs without paid licenses 5 sessions of 2 hours each (Total 10 hours) Complete PPTs, detailed lab manuals, mini project, pre & post quizzes, and all recordings I will ensure the content is beginner-friendly, interactive, and practical. I can share sample slides and lab material for your review before starting. I am confident I can deliver high-quality training that students will understand and enjoy. Looking forward to your positive response. Best Regards, Kudum Yashwanth Mobile: 7019233104
₹25,000 INR in 7 days
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Bengaluru, India
Member since May 24, 2026
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