Ditutup

Get data to an FPGA

6 pekerja bebas membida secara purata $128 untuk pekerjaan ini

liveexperts123

Hi there, I have read your project description and i'm confident i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the Lagi

$155 USD dalam 3 hari
(13 Ulasan)
5.8
vlsirajagopal

having more than 8 years of experience in the field of verilog vhdl design and development. I can do this for you without any functional issues.

$155 USD dalam 3 hari
(22 Ulasan)
5.3
prakashddit

Previously I worked on DMA and scattered gathered DMA from Specifications to RTL. I can provide you architectural ideas to design it.

$35 USD dalam sehari
(7 Ulasan)
3.7
umg536

Hello there, This is a default bid made. we'll discuss the price later in the chat after reading your project i can do this for you perfectly.I still have a few questions. please leave a message on my chat so we can di Lagi

$155 USD dalam 3 hari
(1 Ulasan)
1.8
Subashthesolver

I need more description of what you would like to do. This will be my first project in freelancer if you opt me. I will give my 100 percent to the work assigned. You will never regret your choice.

$111 USD dalam 14 hari
(0 Ulasan)
0.0
aproja

Im Nirob Relevant Skills and Experience Yess im good job

$155 USD dalam 3 hari
(0 Ulasan)
0.0