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Solve a bug on Verilog NetFPGA implementation

We need a Verilog expert to solve a bug on NetFPGA implementation of a modified Ethernet switch. It might be related with timing limitations of the Verilog code to gate conversion handling table writing and reading of MAC addresses at a table. More details on request.

GI

Kemahiran: Elektronik, Verilog / VHDL

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Tentang Majikan:
( 0 ulasan ) Spain

ID Projek: #4067543

10 freelancers are bidding on average €25/hour for this job

MikroStar

hi, i can help.

€45 EUR / hour
(24 Ulasan)
6.1
ahmedmohamed85

Dear sir, I have more than 5 years experince in FPGA programming

€35 EUR / hour
(26 Ulasan)
5.7
botondkireivw

Hello! I can find the bug for you in 4-5 working days (4 hours/day). I expect a 1-2 days of start-up, until I undestand the NetFPGA code and 1-2 to solve the bug. You may check my profile and find there a dosen of Lagi

€20 EUR / hour
(15 Ulasan)
4.6
SanducAndrei

Hi, do you need a professional help?

€20 EUR / hour
(9 Ulasan)
3.3
iZoneFreelancer

Hi, I can do this for you. Good Verilog and FPGA exp. HIGH QUALITY work guaranteed.

€18 EUR / hour
(2 Ulasan)
2.6
taimoortanweer

I know the problem you are facing its just a kind of issue everyone faces. I am capable of doing within hours. Regards

€18 EUR / hour
(0 Ulasan)
0.0
Expert321

Hi I have hands-on experiance on NET-FPGA.............Contact me for Solution I can run it On my Net-FPGA and help to find the bug.

€18 EUR / hour
(0 Ulasan)
0.0
BeyondElectric

I am new to [url removed, login to view], but I have 10+ years of experience with FPGA design as complex as designing a FPGA project that has multiple Nios softcore processors. I have a lot of experiences debugging FPGA issues du Lagi

€30 EUR / hour
(0 Ulasan)
0.0
msk302

I can help you.. i am new to freelancing but have handled many projects earlier.. drop me a personal message with the details so that i can help you out

€20 EUR / hour
(0 Ulasan)
0.0
asicdsm

+20 years of asic/fpga design.

€30 EUR / hour
(0 Ulasan)
0.0