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Verilog Coding Very simple CPU (computer architecture) desig

This is a very very small project. Won't take much time because all design code is already written.

I already have a code. you need to fix some errors in verilog and write 2-3 testbenches and make already written code working (verification should not fail).

More than verilog design, main work is test bench. You should be expert.

Not for someone who want to learn. project should be completed in a day. Not apply if you are not free next 2 days.

Please send me message with your experience with verilog, previous verilog projects and education.

I will send you exact details about project in message.

You should know about computer architecture, pipelining.

Thanks

Actually very simple project. 90% work is done. Budget no more than $50. will give bonus if everything completed on time.

Kemahiran: Kejuruteraan Elektrik, Elektronik, Verilog / VHDL

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Tentang Majikan:
( 3 ulasan ) surat, United States

ID Projek: #1578109

3 pekerja bebas membida secara purata $43 untuk pekerjaan ini

MikroStar

hi, i can help. i am very good in verilog and testbench waveforms.i have recently developed the SINGLE CYCLE MIPS micrprocessor in verilog along with the testbench waveforms. send the project description if you are Lagi

$50 USD dalam 2 hari
(37 Ulasan)
5.9
umarghaffar

hi i can do it please see PMB

$50 USD dalam 2 hari
(3 Ulasan)
2.9
forrestoff

Hi, Funny I'm seeing your post; Four months ago I designed and tested an ATMEGA88 on a spartan 3. I wrote it in VHDL, but I am a stronger verilog designer than I am a VHDL designer. I'm currently a masters stude Lagi

$30 USD dalam sehari
(0 Ulasan)
0.0