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VLSI DESIGN FOR PRODUCT

POWER DELAY OPTIMIZED ADDER FOR MULTIPLY AND ACCUMULATE UNITS

Area: LOW POWER

The prevalent blocks used in digital signal processing hardware are the adder, multiplier and delay elements. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems.

TOOLS USED: TANNER EDA.

A HIGH SPEED 8 TRANSISTOR FULL ADDER DESIGN USING NOVEL 3 TRANSISTOR XOR GATES

Area: LOW POWER

The project proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained.

TOOLS USED: TANNER EDA.

Kemahiran: Elektronik, Verilog / VHDL

Lihat lebih lanjut: VLSI design, vhdl and verilog, systems design, silicon digital systems, prevalent, power systems design, gate design, design hardware, tanner tools, vhdl circuit design, product design factors, design of product, design for product, xor, vlsi, vlsi for, verilog vhdl, silicon, logic design, gate, Electronics Design, eda, digital logic design, digital circuit design, design improvement

Tentang Majikan:
( 0 ulasan ) Mettupalayam-Coimbatore, India

ID Projek: #1526592

2 pekerja bebas membida secara purata ₹35000 untuk pekerjaan ini

hdlveca

Hi, I have been ASIC Engineer for over than three years. Looking forward hearing from you. BR

₹30000 INR dalam 30 hari
(4 Ulasan)
3.7
ee4raja

Hi, I have 4 years of experience in VLSI domain including design, verification and FPGA bring up. Thanks,

₹40000 INR dalam 15 hari
(3 Ulasan)
3.7