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fail during FPGA loading

I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP core to reduce the input board clock from 100 MHz down to 2 MHz which drives a Unique Chip ID core. It also blinks an LED on the board.

You can download the project here: [login to view URL]

The code works fine and I can see the blinking LED. However, if I un-comment line 59 in [login to view URL], the chip programming would fail at 85% (attached image).

How to fix the issue?

Kemahiran: Kejuruteraan Elektrik, Elektronik, FPGA, Verilog / VHDL

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Tentang Majikan:
( 2 ulasan ) Alexandria, United States

ID Projek: #17280348

5 pekerja bebas membida secara purata $106 untuk pekerjaan ini

ahmedmohamed85

Dear sir I have more than10 years experience in digital design using fpga please check my profile also please message me so that we can discuss

$111 USD dalam sehari
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7.7
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Lagi

$100 USD dalam 0 hari
(72 Ulasan)
6.1
RushService

Feel fee to contact me for fail during FPGA [login to view URL] me message to discuss further more details .We provide the commments,images,videos,demos and live sessions in order to help the [login to view URL] payment only af Lagi

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giridharreddy16

Hi I am an Electronics engineer with industry experience of 3 years. Dealing with electronics projetcs at various levels like architecture, design, RTL, schematics, layout and validation of the product. Your problem se Lagi

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