The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC.
As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.
Already done a such work for the TI ADS5402 800MSPS pipeline ADC, but I need to know, which ADC exactly you use and do you need specific interface (AXI4-Stream or smth like that) as output.
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Hello, there i am krishna from LogicTronix [An FPGA Design Company]. I have expertise on the FPGA design with high speed ADC. Let me know your project details!