Innovus VLSI P&R Guidance

I am taking my first real dive into physical design with an open-source PicoRV32 core I cloned from GitHub. So far I have completed the basic floorplan, power grid, and initial placement, but once I move into placement-and-routing inside Innovus the run ends with a long list of DRC violations that I am struggling to interpret and fix. The goal is to finish a clean, sign-off-quality layout while learning industry-standard methodology along the way. I already have access to Genus for synthesis, Innovus for P&R, PrimeTime for STA, and Tempus for sign-off timing; what I lack is the practical know-how to connect the dots, tune the tool settings, and understand the reports. What I need from you • Live or asynchronous guidance focused on Innovus placement and routing, especially strategies to eliminate post-route DRCs. • Review of my current scripts, constraints, and environment files, with explanations of why certain switches or flows matter. • Advice on correlating Innovus, PrimeTime, and Tempus reports so timing closure does not reopen after each iteration. • Quick checkpoints on any related steps (floorplan refinement, power planning tweaks) whenever they block progress. The engagement will be hands-on: I share logs, screenshots, or the design database; you point out the root causes, demonstrate fixes, and suggest best practices I can reuse on future projects. If this matches your expertise in advanced physical design, let’s connect and start clearing those DRCs.

ID Projek: 40338873