Ditutup

Implementation of Left looking LU decomposition Algorithm onFPGA using verilog - open to bidding

firstly i want a design only...i will show that to my head...if he is ok with that then we will proceed with the code and simulation the verify results

Kemahiran: Kejuruteraan Elektrik, Elektronik, Kejuruteraan, Mikropengawal, Verilog / VHDL

Lihat lagi:

Tentang Majikan:
( 3 ulasan ) mumbai, India

ID Projek: #10098782

4 pekerja bebas membida secara purata $24/jam untuk pekerjaan ini

$22 USD / jam
(123 Ulasan)
6.6
$25 USD / jam
(3 Ulasan)
2.6
sindhuchalla

Hi, I am an experienced VLSI engineer with strong verilog and FPGA architecture knowledge. I can deliver design with in a day or 2 after getting the material. I hope I can fulfill your need for the project.

$25 USD / jam
(0 Ulasan)
0.0
CSivaRam

I will provide the design within a one week. Simulation and results would take another two weeks. Total time frame is 3 weeks * 10 hours per week.

$22 USD / jam
(0 Ulasan)
0.0