Have a design that is synthesizable and works properly on FPGA (nexys video - artix-7 based).
The clock is set via clock wizard, and I need to make it flexible without the need to regenerate bistream every time.
The dynamic clock setting can be done via "sw" pins (nexys video has 8 sw pins on board).
When new clock frequency is set, the expectation that design will reset and restart operation once the new clock frequency is stable.
Bonus - If you can also enable this flexibility via python script when FPGA is connected with USB (so the clock control registered will be programmed directly from PC).
17 pekerja bebas membida secara purata $234 untuk pekerjaan ini
Hi Its possible to do this so that you can configure the clock from a pc. That way you can set any frequency you want within the range of the MMCM. Regards Jon
Hello, I have read the details provided and i am positive i can provide quality work,please contact me to discuss more on the project deadline and some other few things
Wow, Wonderful! I met the first FPGA project in freelancer :) I am FPGA (VHDL) expert! so I can help you. I 'd like discuss with you via chatting. I will wait. Thank you! From Apollo!~