Verification IP development for AXI Protocol using system Verilog

VIP component development for AXI3.0 protocol with support for various features like burst type, burst size, protection, out of order, overlapping, aligned,WRAP,fixed burst . Develop BFM, Generator, Monitor, and Coverage models and also the slave model.

Kemahiran: Pengaturcaraan C, Pengaturcaraan C++, FPGA, Kejuruteraan Perisian, Verilog / VHDL

Lihat lebih lanjut: axi master verilog code, axi uvm vip, axi protocol verification using uvm, axi protocol verification, axi protocol verilog code, address resolution protocol using java, write podem algorithm using verilog, file transfer protocol using hybrid encryption eap tls, vlsi circuit design using verilog, rtl design using verilog, design development inventory management using struts framework, cisco router design using verilog, code deframer using verilog, reverse polish notation calculator using verilog, controller design using verilog hdl

Tentang Majikan:
( 0 ulasan ) Chennai, India

ID Projek: #15529477

5 pekerja bebas membida secara purata ₹11155 untuk pekerjaan ini


Hello! Please check my profile and reviews to know a bit about me and my work. Hope you would contact to discuss further. Thank you! Relevant Skills and Experience Verilog - 3+ years AXI Protocol - 2+ years SV/UVM - 2 Lagi

₹13888 INR dalam 15 hari
(77 Ulasan)

Creation AMBA AXI master VIP to verify slave model with unaligned,burst,wrap supports. Relevant Skills and Experience Have created AXI master VIP using SV UVM when I verified DMA on ethernet switch. Having good knowle Lagi

₹13888 INR dalam 15 hari
(1 Ulasan)

i can develop this for you Relevant Skills and Experience i have an experience of 1.5-2 years in this field Proposed Milestones ₹8000 INR - 1 sir i did projects like this kindly reply i want to discuss it with you

₹8000 INR dalam 4 hari
(1 Ulasan)

I'll create VIP for AXI with master and slave modes in constrained verification random environment. If UVM is ok, i'll base that testbenc on UVM. Relevant Skills and Experience Expert System verilog knowledege, many y Lagi

₹7777 INR dalam 5 hari
(0 Ulasan)

I would be able to finish this proficiently as I have know this protocol well and my current project also involves this project. Relevant Skills and Experience I am working as a Sr. ASIC Verification Engineer in one o Lagi

₹12222 INR dalam 15 hari
(0 Ulasan)