I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module with Verilog such as Convolution En
$224 USD / jam
7 pekerja bebas membida secara purata $59/jam untuk pekerjaan ini
We have 20 years of strong experience in Verilog / VHDL, Software Architecture, Electrical Engineering, as a result, we can successfully complete this project.
Please, review our profile here: httpsLagi
I am a fourth-year student from the Department of Electronics and Electrical Communication Engineering. This is the domain of my interest. I shall be able to do this in a few hours. I have more than 12 months of continLagi