Ditutup

Encoding ,modulation/digital modelling

7 pekerja bebas membida secara purata £186 untuk pekerjaan ini

xaainulabideen

For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail.

£135 GBP dalam 7 hari
(16 Ulasan)
5.0
etalhak

Hello, I am an electronics and telecommunication engineer and my major is wireless sytsems' systems' design. I have a solid background in telecommunication theory. I have checked your requirements and I am sure that I Lagi

£150 GBP dalam 7 hari
(21 Ulasan)
4.7
Valuesolutions

Hello, I hope this finds you well. I have just seen your project requiring; Verilog / VHDL Telecommunications Engineering Circuit Design Simulation Analog / Mixed Signal / Digital I believe that my 10-year experience Lagi

£135 GBP dalam 7 hari
(5 Ulasan)
4.3
senthilps3

Hi I have the experience about the project of introduction of clock jitter in Tx and it is recovered in Rx. In Verilog modeling, PLL, DLL and Manchester encoding/decoding were created and verified. This project is a Lagi

£250 GBP dalam 10 hari
(11 Ulasan)
3.3
hsh564cf84accd96

We will do your work Hi my Professional Aim is: (Services then Solutions then Satisfactions) I hope you are [login to view URL] an experience in this field from last 5 years i am sure i can do it perfectly with in a time and bu Lagi

£135 GBP dalam 7 hari
(4 Ulasan)
3.2
yanatejaip5s

I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module with Verilog such as Convolution En Lagi

£300 GBP dalam sehari
(1 Ulasan)
1.3
WeGlobalEnt

Hello, I am an electronics and telecommunication engineer and my major is wireless sytsems' systems' design. I have a solid background in telecommunication theory.

£200 GBP dalam 7 hari
(0 Ulasan)
0.0