i can do it in modelsim....
i have 2.5+ year experience in design and verification,
i have done 30+ project in verilog/VHDL,
i will done your project perfectly and on time,
i will provide support after completion ofLagi
Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and FSM and had a working eLagi