I need Verilog design

Project Rules:

You will design a significant project on the DE1boardand.

•Use Verilog statements from the “Verilog Tutorial” given.

•Prototyping board :The labeled pins (Figure 1) are connected to the FPGA and usable. You can access these pins using a bus connection of “”(in/out for input/output)to your top-level module (similar to , , in previous labs). is the leftmost connection (), and is the rightmost connection ().

•16×16Bicolor LED Expansion Board: See the “LED Board” tutorial and 4 files as given for usage and getting started.

•Multiple “clock speeds”: Your entire circuit should use a single clock –either or one of the outputs from circuit. If you need multiple clock trigger speeds, first set the clock to the fastest speed that you need and then use a counter to generate a slower signal. All slower elements/modules will still use the faster clock, but will only change state when the slower counter signal occurs.


1)How does someone use/operate/play your design?

2)A block diagram of your entire system with a brief description of the interconnections.

3)A brief description of each module you created and its purpose. For modules that include finite state machines, include a state diagram for each one. Include ModelSim simulation results that reasonably prove each module’s correct behavior.

4)Briefly describe how you went about testing your system.

Project: Flappy Bird

Flappy Bird ( [login to view URL]) has our hero the Caped Cardinal (a red dot) flapping through a maze of “pipes” (green vertical lines).


•The hero will “move forward” through a maze of randomly-generated pipes at a constant speed.

•Single button input: The red dot goes up when the button is pressed and down when the button is released.

•The user’s goal is to avoid the pipes for as long as possible by flying through the gaps.

•Your system should track and display the user score. Be prepared to display a score up to at least 999.

Kemahiran: Verilog / VHDL, FPGA, Reka Bentuk Digital

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Tentang Majikan:
( 0 ulasan ) Bellevue, United States

ID Projek: #28344508

5 pekerja bebas membida secara purata $140 untuk pekerjaan ini


A FPGA/IC design expert with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Lagi

$30 USD dalam 5 hari
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Hello, I am an FPGA deign engineer having experience of verilog based system design for more than 5 years.

$140 USD dalam 2 hari
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(3 Ulasan)

Hello, Hope this message finds you well, I checked your details and I believe that my experience is what you are looking 4. I have been working on similar projects for the past eight years, and I have the essential sk Lagi

$250 USD dalam 3 hari
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This is the my first project so I hope to take it. Work since 2001 in the design of complex digital ASICs with a complete view on all the design flow: form system specification to the layout. I am able in system spe Lagi

$30 USD dalam 14 hari
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