SERDES Interface - open to bidding

Implement a Serdes a full duplex communication system between two microcontrollers, with 16 datablock buffering. The Serdes implemenation will also include auto sync lock. Data will be passed in 16 byte blocks, with interface to the microcontollers being 16 bit

Kemahiran: Verilog / VHDL

Lihat lagi: verilog vhdl, system verilog, implement interface, implemenation, microcontrollers vhdl, verilog bidding, data communication system

Tentang Majikan:
( 9 ulasan ) Taipei, China

ID Projek: #5494674

Dianugerahkan kepada:


A proposal has not yet been provided

£35 GBP / jam
(127 Ulasan)

6 pekerja bebas membida secara purata £29/jam untuk pekerjaan ini


Hello! If you have digital design project I can help you right away! I have 8 years experience in designing digital logic circuits using VHDL and implementing them in FPGA. I was a digital design engineer at Grenoble I Lagi

£22 GBP / jam
(20 Ulasan)

Hello, I have a long (16+ yeards) experience in FPGA based development for telecom products. I have used Xilinx, Altera and Lattice FPGAs. I am conversant with VHDL and verilog. I assume this project for communicati Lagi

£27 GBP / jam
(1 Ulasan)

I worked as Research Assistant on the project "Secure Dial" and my task is to communicate between FPGA and modem through serial cable RS232. I also did encryption AES 256 on FPGA. I have strong programming in verilo Lagi

£22 GBP / jam
(0 Ulasan)

I offer you 30 year in electronics, expertise and experience outsourcing FPGA design services since 1996. We are well established company. We have the know-how implementing high speed serial link. Deliveries : Sourc Lagi

£36 GBP / jam
(0 Ulasan)

 9+ years of work experience in high speed FPGA based Digital Logic Design and Development using VHDL.  Implementation and debugging in various device families FPGA.  Functional and Timing verification using MODE Lagi

£30 GBP / jam
(0 Ulasan)