A Simple State Machine including Test bench and memory block

Implement a simple state machine that controls the sequencing of the line LdA, LdB and LdS. The objective is to enable each of these at

successive clock cycles such that you are able to load register A in cycle 1, then B in cycle 2 and to examine the result in cycle 3. See the

timing diagram below

The DE1 board includes an SRAM chip, called IS61LV25616AL-10, a static RAM with a

capacity of 256K 16-bit words

Kemahiran: Verilog / VHDL

Lihat lagi: simple state machine, vhdl and verilog, test board, 3 line diagram, a simple c, verilog vhdl, state, load test, load board, chip a, block diagram clock, state machine, state diagram, vhdl register, de1 sram chip, bench, examine, simple objective, sram is61lv25616al, sram de1, de1, test bench state machine, sram de1 board, sram vhdl, line diagram

Tentang Majikan:
( 1 ulasan ) Frankston, Australia

ID Projek: #1584325

Dianugerahkan kepada:


i will do it now

$50 AUD dalam sehari
(23 Ulasan)

2 pekerja bebas membida secara purata $113 untuk pekerjaan ini


hi, I have good knowledge of the VHDL and Verilog. I can do its fast as you required.

$175 AUD dalam 7 hari
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