>>That is, convert input from serial to parallel, store data in RAM, take data from ram and send to

other data lines.

>>6-8 input detector-> counter value "4" puts data in to ram, then serial to paralel converter put in


>>d1 d2 d3 bytes to decode and then sepearte data from d1 d2 d3 to other data bus.

>>90 lenth, 90 width, is the frame size. LFSR is the data source.

1) COnvert shift register to incorportate frame detect ckt. (vhdl code)

hint: 16bit shift reg. start SR code. add decode vhdl code to detect frame:

F628 is the pattern of the code we're detecting.

Process; to be able to decode this circuit , we need a a testbench.

2) bit counter: 0-7: (Use frame detect)

3) byte counter: 0-809 (Use frame detect)

Please take a look and let me know what yu think.

Kemahiran: Verilog / VHDL

Lihat lagi: sonet vhdl, parallel serial vhdl code, vhdl code detect sonet frame, data frame vhdl code, data frame vhdl, sonet frame vhdl, vhdl code sonet, vhdl and verilog, frame store, 16bit shift register vhdl, yu, vhdl, verilog vhdl, sr, look frame, detector, byte, decode data, bit vhdl counter, convert vhdl verilog, vhdl register, vhdl bit counter, bit pattern, Sonet , vhdl counter code

Tentang Majikan:
( 2 ulasan ) Mumbai, United States

ID Projek: #1545517

2 pekerja bebas membida secara purata $250 untuk pekerjaan ini


Hi, I have 4.4 years of experience in VLSI domain including design, verification and FPGA bring up. Looking forward for your favor reply

$250 USD dalam sehari
(2 Ulasan)

Nice to meet you, I am holding experience and knowledge in the digital design field. Kindly consider me to do this project.

$249 USD dalam 3 hari
(0 Ulasan)