Looking for assistance in verilog HDL for design of SRAM and HDMI controller. Specifically, designing verilog code to take incoming data, put the data into a FIFO SRAM, pass the data through an RGB encoder, then to an HDMI encoder, and finally out to an HDMI screen. Alternatively, would like to achieve the same system using pipelining to synchronize clocks of the input and output using a shallow BRAM on the FPGA.
To give you a little more background, the input would be two video data lines totaling 4 bits to be stored in the FIFO SRAM, then put through an RGB encoder to colorize each bit, then given to the HDMI controller to be sent out.
Ultimately, I would like the code to be ported to xilinx XC3S200.
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Electronics Engineer with experience in large scale complex systems development with practicing in Verilog, SystemVerilog and Programming Firmware, C, C++. Let's Discuss further.
Hi, I have been working with FPGA designs in verilog since 21 years. Currently I am working on 2 projects based on Spartan6 and Kintex7 both of which are for Displays. I have been working on several video standards.
Hello Employer When I was Electrical engineering student I always did projects like this. I have approx one year experience of fpgas. If you choose me you'll never regret.