I need to make an ALU that can make an output using data_in from an tester .. also the data in can be an header on payload acordoing from 2 other signals
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Hello , I am a FPGA design engineer with 2 years of experience. I have gone through your code, I can write the logic. I will provide you updated testbench for the whole project. We can negotiate the price. Thank You.
I am a RTL designer, worked on Projects like Network on Chip, Speech and Image Processing, using Verilog/VHDL. I even work on Chipscope Pro and System Generator on Xilinx ISE and Xilinx Vivado.