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VHDL / Verilog coding for Altera Native PHY

Looking for person with background in VHDL or Verilog and experience with Altera Quartu software and Altera IPs. This job is about debugging/configuring Native PHY for use with SATA protocol. We have most of the design, but some low-level Altera IP configuration is not working correctly. Can provide FPGA board we are using for debugging (within US) if needed. This should be a very quick project for someone familiar with Altera Native PHY and IPs.

Kemahiran: Verilog / VHDL

Lihat lagi: vhdl and verilog, verilog job

Tentang Majikan:
( 17 ulasan ) Malerkotla, India

ID Projek: #10107839

6 pekerja bebas membida secara purata $701 untuk pekerjaan ini

ibnuhasan

I have worked in USB 3.0 IP with altera, basically I'm in India, is it possible to ship board?

$888 USD dalam 30 hari
(0 Ulasan)
0.0
guruuvce12

Kind of work done in the past and teaching same subject from so many year. My knowledge and experience will help me to finish your project very effectively and meeting with deadline. For any clarification pls do cont Lagi

$1111 USD dalam 6 hari
(0 Ulasan)
0.0
achievemani

Cumulative experience of 30 years VLSI professionals, would like to work in exciting projects like this.

$277 USD dalam 7 hari
(0 Ulasan)
0.0
$555 USD dalam 10 hari
(0 Ulasan)
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$777 USD dalam 7 hari
(0 Ulasan)
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jvivekp

Sir/Mam, I have extensive experience in the VLSI domain (7.5 years) in front design and implementation of SoCs, ASICs and FPGA implementations. Do feel free to communicate with me in case you need additional inform Lagi

$600 USD dalam 7 hari
(0 Ulasan)
0.0