VHDL / Verilog coding for Altera Native PHY

Looking for person with background in VHDL or Verilog and experience with Altera Quartu software and Altera IPs. This job is about debugging/configuring Native PHY for use with SATA protocol. We have most of the design, but some low-level Altera IP configuration is not working correctly. Can provide FPGA board we are using for debugging (within US) if needed. This should be a very quick project for someone familiar with Altera Native PHY and IPs.

Kemahiran: Verilog / VHDL

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Tentang Majikan:
( 0 ulasan ) United States

ID Projek: #10105128

4 pekerja bebas membida secara purata $1063 untuk pekerjaan ini


Dear sir I have more than 9 years experience in digital design using vhdl, please check my profile also please message me so that we can discuss Best regards

$1556 USD dalam 7 hari
(347 Ulasan)

Hello! How are you!? I have 5 years experience with Altera Quartus and VHDL. I can help you right away! Please send me a message with all the details! Have a nice day!

$750 USD dalam 5 hari
(44 Ulasan)

Kind of work done in the past and same subject teaching in my regular academic so it will help me to finish your project very effectively if you need any clarification contact me.

$1111 USD dalam 5 hari
(0 Ulasan)

Cumulative experience of 30 years experienced VLSI professionals. Would like to work in exciting projects like this.

$833 USD dalam 10 hari
(1 Ulasan)