Vlsi testing and verification using Synopsis EDA for sequential circuits

Firstly I would need a project suggestion for a masters project in VLSI testing and verification using Synopsis EDA tools for sequential circuits, because I have to submit a project proposal.

Once a project suggestion seems acceptable, I will need help in finishing the project with desired outputs and compare the same with FPGA implementation.

By bid for project is 700$

Kemahiran: FPGA, Verilog / VHDL, Very-large-scale integration (VLSI)

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Tentang Majikan:
( 1 ulasan ) Fresno, United States

ID Projek: #15939734

10 pekerja bebas membida secara purata $562 untuk pekerjaan ini


Dear sir I have more than 10 years experience in digital design using FPGA and VLSI design, I suggest creating AES circuit available in IEEE paper, and perform testing and simulation Best regards

$777 USD dalam 10 hari
(310 Ulasan)

Hello! Please check my reviews and profile to know more about me and my work. Hope you’d contact to discuss further. Thank you!

$700 USD dalam 10 hari
(51 Ulasan)

hi, i can help you in VLSI testing project and sequential circuit design Relevant Skills and Experience Electrical Engineer Proposed Milestones $500 USD - Sequential Circuit Desgin

$500 USD dalam 5 hari
(31 Ulasan)

Verification project on current methodology on EDA synopsys vcs tool. Relevant Skills and Experience Having more than 7 years of industry experience on verirification using system verilog UVM Proposed Milestones $555 Lagi

$555 USD dalam 10 hari
(6 Ulasan)

have expertise in RTL Digital Logic Design for 2.5+ years

$333 USD dalam 5 hari
(2 Ulasan)

Dear Sir How are you? Merry Chrismas!! I am an VLSI design expert. I can surely complete your project on time. I am sure that the result is the first. Thanks for reading my bid. Issak vetter Relevant Skills and Exper Lagi

$277 USD dalam 10 hari
(2 Ulasan)

We have experienced in Synopsys EDA tools and we have access to the licensed tools to carry out the task. Relevant Skills and Experience Verilog, VHDL, Design Compiler Primetime VCS Formality RTL Desing and Verificat Lagi

$666 USD dalam 10 hari
(0 Ulasan)

I have well experienced in doing such kind of jobs........................ Relevant Skills and Experience verilog/vhdl Proposed Milestones $700 USD - i will do my level best

$700 USD dalam 3 hari
(0 Ulasan)

I expert in VCS. ReWrite your design in System Verilog. Time deponds on your project.

$777 USD dalam 7 hari
(0 Ulasan)
$333 USD dalam 10 hari
(0 Ulasan)