Imej profil Elecguru011
Penanda Pakistan Rawalpindi, Pakistan
Ahli semenjak 16 Oktober 2011
0 Cadangan


Dalam Talian Luar Talian
I specialize in Field Programmable Gate Array design , I have developed numerous VHDL/Verilog ip cores that have been integrated in high performance embedded systems, Nios SOC , ARM SOC, Digital Signal Processing and Image Processing. I also have extensive experience in test and verification of FPGA designs using Tcl and VHDL/Verilog Testbenches. Multilayer PCB design is also my expertize. #PLEASE IGNORE COMMENTS FROM "Mohammad.K" linked to Wishbone bus . He dealt the project work unprofessionally and used very pathetic language. After setting a milestone he demanded/begged for incomplete report before delivery date and criticized me for not delivering as promised. He is very difficult person to work with and it is very confusing and hard to understand his communication.
$5 USD/hr
1 ulasan
  • N/AKerja Diselesai
  • N/AMengikut Bajet
  • N/ATepat Pada Masa
  • N/AKadar Ulang Upah


Ulasan Terkini

  • Imej Muhammad K. Wishbone bus and Can bus $50.00 USD

    “He is a real rascal. Do not pay this buttered before he delivers. he dose not know nothing will grab money from you and will not even than replay. Do not release the milestone whatever they say.”


Project Engineer

Jul 2015

Embedded Systems design , FPGA and PIC Microcontroller based hardware design . Firmware and Software design and Systems analysis using Matlab.

Team Lead

Jan 2012 - Dec 2014 (2 years)

I worked as Hardware Design group Team Lead , developed modules for wireless sensor network.

Digital and Analogue Design Engineer

May 2010 - Dec 2011 (1 year)

FPGA Hardware Design of Satellite Communication system.

FPGA Design Engineer

Feb 2006 - Dec 2008 (2 years)

OTDR implementation on a FPGA , Moving Averaging Filter design .

Design Engineer

Sep 2001 - Nov 2005 (4 years)

FPGA Design for MIL-STD-1553 and front end circuit design.


MSc Electronics Engineering

1998 - 2001 (3 years)

M.Sc Telecommunication Engineering

2015 - 2017 (2 years)


Winner Best Design (2004)

Cypress Semiconductor

Reconfigurable Logic using PSOC

DSP Systems Engineering (2012)

University of California , Irvine

Digital Signal Processing fundamentals, DFT,FFT , Digital Filter modelling and simulation using Matlab, FIR and IIR filter implementation on FPGA


Audio Signal Processing

An audio signal frequency range is from 20Hz to 20Khz. In a music sample 20Khz bandwidth is required to encompass all harmonics. Although natural sounding speech only requires about 3.2Khz . Telecommunication systems typically operate with a sampling rate of about 8 kHz, allowing natural sounding speech, but greatly reduced music quality. \n\nHere we are proposing a FPGA based audio signal filtering system which is reconfigurable and can be used as a Processing Engine to reduce background noise from a musi

OTDR Implementation on FPGA

Optical Time Domain Reflectrometery\n\nIn optical fiber communication, optical time domain reflectometery (OTDR) is a commonly used technique for characterization and fault location of optical fiber transmission systems. It involves measuring the fraction of a probe pulse that is scattered back (by Rayleigh scattering) from a silica fiber. Because of the very small levels of backscatter in single-mode fiber at long wavelengths, very sensitive optical detection is necessary to achieve adequate range performa


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