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Anju G.

@anjugup

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M.Tech in VLSI

Bendera

India (9:07 PTG)

Menyertai pada Mac 16, 2007

Graduate in VLSI, and having cutting edge exposure from minarc, ISEP, Paris in microelectronics. I am here to broaden the horizon of the challenges. I have published a paper in IEEE-TED.

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Ulasan

Tiada ulasan untuk dilihat di sini!

Pengalaman

Contract engineer

Okt, 2007 - Jun, 2008

8 bulan

DRDO

Okt, 2007 - Jun, 2008

8 bulan

I was involved and evolved in developing in web pages and developing the online web pages for the company.

Okt, 2007 - Jun, 2008

8 bulan

Pendidikan

Vellore Institute of Technology

2008 - 2010

2 tahun

M.Tech

Bendera

India

2008 - 2010

2 tahun

Visvesvaraya Technological University

2002 - 2006

4 tahun

B.E.

Bendera

India

2002 - 2006

4 tahun

Kelayakan

Designing

2010

Paper publishes in designing in IEEE-TED

2010

Penerbitan

30nm Tunnel FET with Improved Performances and Reduced Ambipolar Current, published in IEEE-TED (Transaction on Electron Device), TRANSACTIONS ON ELECTRON DEVICES

Anju Gupta

To boost the on current with the source edges.

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