Duc D. Profile

5.0

(110 ulasan)

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E-mel berjaya disahkan.

$40 USD / jam

hanoi,

vietnam

$40 USD / jam

Sekarang ini 5:24 PTG di sini

Menyertai pada Mei 14, 2015

4 Syor

Duc D.

@ducdctoandh

5.0

(110 ulasan)

7.1

$40 USD / jam

hanoi,

vietnam

$40 USD / jam

100%

Pekerjaan Disiapkan

98%

Mengikut Bajet

99%

Tepat Pada Masa

17%

Kadar Upah Semula

Electronics Engineer

6 YEAR EXPERIENCE IN FPGA/VHDL/VERILOG - 100% JOB COMPLETED - COMPLETED ABOVE 100 JOBS IN FPGA/VHDL/VERILOG - 87 VERY GOOD REVIEWS I am an electronics engineer with excellent academic background, firm language skills (IELTS 6.0) and 5-years experience in TOP SKILLS below (Graduated Very Good Degree - Top 5% graduated Student at Top University in Vietnam) TOP SKILLS 1. FPGA Design. (VHDL/Verilog) 2. Embedded System Design. (Schematic, PCB Design) 3. Software Design. (C/C++/Java/Android/Matlab) TOOLS 1. Xilinx Vivado/Xilinx ISE/IP Core of Xilinx. 2. Altium/Orcad/KidCad design. 3. DevC++/Visual Studio C/C++/Eclipse/Netbeen. 4. Matlab/LabView LANGUAGES -English: IELTS 6.0 (Reading 6.5, Speaking 6.5, Writing 6.0, Listening 5.5)

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Item Portfolio

Technical Report

This is the project to take data from Camera and transfer to FPGA and display into the HDMI monitor. In FPGA, we implement the algorithm to detect human in the picture and report in monitor.

Walker Recognition project

This is low-cost multiplier that I implemented in Verilog. The pictures are the simulation for 34x34 bit, 51x51 bit, 66x66 bit.

Quadruple Precision Karatsuba Multiplier

Ulasan

Perubahan disimpan

Menunjukkan 1 - 5 daripada 50+ ulasan

Tapis ulasan mengikut:

5.0

$6,000.00 USD

Zync DRAM Project -- 2

Duc is the one of the best Engineers I have ever worked with. He is absolutely the person you can trust to get your project done.

C Programming

FPGA Coding

John S.

@jmichael1234

•

11 bulan yang lalu

5.0

$450.00 USD

Project 32189922 has been deleted

Master class, he was available all the time for any questions or explanations about the project. Everything done perfectly!

Matej P.

@MatejPetrovic

•

1 tahun yang lalu

5.0

£4,400.00 GBP

FPGA design port to Xilinx Zynq

Duc worked helped to port a design from a Max10 FPGA to a Xilinx FPGA, he has communicated well and shown great tenacity to get the job done. He has great skills and expertise in FPGA design and has enabled me to significantly improve my products performance. From the project planning stage he was very helpful and willing to make very useful suggestions. If you have a complex FPGA design project I would recommend you contact Duc

Electronics

Verilog / VHDL

FPGA

John P.

@JohnPRed

•

1 tahun yang lalu

5.0

$300.00 USD

VHDL 4 Stage Pipeline Design

Was a pleasure working with him again, his budget was reasonable and he was able to complete the project in the given time frame. Would recommend him for any project you may have

Engineering

Electronics

Verilog / VHDL

Electrical Engineering

Circuit Design

Ishabul H.

@ishue

•

2 tahun yang lalu

5.0

$56.00 USD

FPGA project

Very easy to communicate with.

Electronics

Verilog / VHDL

Microcontroller

Electrical Engineering

FPGA

Mark L.

@ozmataz

•

2 tahun yang lalu

Pengalaman

Applistar

Okt 2014 - Hari ini

Design FPGA/IC using Verilog/VHDL Hardware Description Language

Apr 2014 - Okt 2014 (6 bulan, 1 hari)

Contact customers to fix customer’s issue in some HP software

Pendidikan

Very Good

Truòng Dai hoc Bách Khoa Hànôi,

Vietnam

2009 - 2014

(5 tahun)

Kelayakan

2013

Networking Management

Penerbitan

A Generalized Link Sharing and Resource Allocation Framework for Multi-Layer Virtual Networks based on SDN

Thanh Nguyen Huu, Anh-Vu Vu, Dipl.; Cong-Duc Duong, Dipl.; Duc-Lam Nguyen, Dipl.; Manh-Nam Tran, M.Sc.; Quynh-Thu Ngo, Dr.; Tai-Hung Nguyen, Dr.; Thomas Magedanz, Prof. Dr.

An OpenFlow protocol to control traffic in network