Logo Freelancer Bagaimana Ia BerfungsiLayari Pekerjaan Log Masuk Daftar Siarkan ProjekProfile cover photo
Anda sekarang mengikuti .
Ralat mengikuti pengguna.
Pengguna ini tidak membenarkan pengguna untuk mengikuti mereka.
Anda telah mengikuti pengguna ini.
Pelan keahlian anda hanya membenarkan 0 mengikuti. Naik taraf di sini.
Berjaya tidak mengikuti pengguna.
Ralat tidak mengikuti pengguna.
Anda berjaya mengesyorkan
Ralat mengesyorkan pengguna.
Sesuatu telah berlaku. Sila segar semula halaman dan cuba lagi.
E-mel berjaya disahkan.
Avatar Pengguna
$40 USD / jam
Bendera VIETNAM
hanoi, vietnam
$40 USD / jam
Sekarang ini 5:24 PTG di sini
Menyertai pada Mei 14, 2015
4 Syor

Duc D.

@ducdctoandh

annual-level-one.svgverified.svg
5.0 (110 ulasan)
7.1
7.1
$40 USD / jam
Bendera VIETNAM
hanoi, vietnam
$40 USD / jam
100%
Pekerjaan Disiapkan
98%
Mengikut Bajet
99%
Tepat Pada Masa
17%
Kadar Upah Semula

Electronics Engineer

6 YEAR EXPERIENCE IN FPGA/VHDL/VERILOG - 100% JOB COMPLETED - COMPLETED ABOVE 100 JOBS IN FPGA/VHDL/VERILOG - 87 VERY GOOD REVIEWS I am an electronics engineer with excellent academic background, firm language skills (IELTS 6.0) and 5-years experience in TOP SKILLS below (Graduated Very Good Degree - Top 5% graduated Student at Top University in Vietnam) TOP SKILLS 1. FPGA Design. (VHDL/Verilog) 2. Embedded System Design. (Schematic, PCB Design) 3. Software Design. (C/C++/Java/Android/Matlab) TOOLS 1. Xilinx Vivado/Xilinx ISE/IP Core of Xilinx. 2. Altium/Orcad/KidCad design. 3. DevC++/Visual Studio C/C++/Eclipse/Netbeen. 4. Matlab/LabView LANGUAGES -English: IELTS 6.0 (Reading 6.5, Speaking 6.5, Writing 6.0, Listening 5.5)
Freelancer Verilog / VHDL Designers Vietnam

Hubungi Duc D. mengenai pekerjaan anda

Log masuk untuk membincangkan sebarang butiran melalui sembang.

Item Portfolio

Technical Report
Technical Report
This is the project to take data from Camera and transfer to FPGA and display into the HDMI monitor. In FPGA, we implement the algorithm to detect human in the picture and report in monitor.
Walker Recognition project
This is low-cost multiplier that I implemented in Verilog. The pictures are the simulation for 34x34 bit, 51x51 bit, 66x66 bit.
Quadruple Precision Karatsuba Multiplier
This is low-cost multiplier that I implemented in Verilog. The pictures are the simulation for 34x34 bit, 51x51 bit, 66x66 bit.
Quadruple Precision Karatsuba Multiplier
This is low-cost multiplier that I implemented in Verilog. The pictures are the simulation for 34x34 bit, 51x51 bit, 66x66 bit.
Quadruple Precision Karatsuba Multiplier

Ulasan

Perubahan disimpan
Menunjukkan 1 - 5 daripada 50+ ulasan
Tapis ulasan mengikut: 5.0
$6,000.00 USD
Duc is the one of the best Engineers I have ever worked with. He is absolutely the person you can trust to get your project done.
C Programming FPGA Coding
J
Bendera John S. @jmichael1234
11 bulan yang lalu
5.0
$450.00 USD
Master class, he was available all the time for any questions or explanations about the project. Everything done perfectly!
M
Bendera Matej P. @MatejPetrovic
1 tahun yang lalu
5.0
£4,400.00 GBP
Duc worked helped to port a design from a Max10 FPGA to a Xilinx FPGA, he has communicated well and shown great tenacity to get the job done. He has great skills and expertise in FPGA design and has enabled me to significantly improve my products performance. From the project planning stage he was very helpful and willing to make very useful suggestions. If you have a complex FPGA design project I would recommend you contact Duc
Electronics Verilog / VHDL FPGA
J
Bendera John P. @JohnPRed
1 tahun yang lalu
5.0
$300.00 USD
Was a pleasure working with him again, his budget was reasonable and he was able to complete the project in the given time frame. Would recommend him for any project you may have
Engineering Electronics Verilog / VHDL Electrical Engineering Circuit Design
Avatar Pengguna
Bendera Ishabul H. @ishue
2 tahun yang lalu
5.0
$56.00 USD
Very easy to communicate with.
Electronics Verilog / VHDL Microcontroller Electrical Engineering FPGA
O
Bendera Mark L. @ozmataz
2 tahun yang lalu

Pengalaman

Programmer

Applistar
Okt 2014 - Hari ini
Design FPGA/IC using Verilog/VHDL Hardware Description Language

IT Supporter

HP
Apr 2014 - Okt 2014 (6 bulan, 1 hari)
Contact customers to fix customer’s issue in some HP software

Pendidikan

Very Good

Truòng Dai hoc Bách Khoa Hànôi, Vietnam 2009 - 2014
(5 tahun)

Kelayakan

CCNA

2013
Networking Management

Penerbitan

A Generalized Link Sharing and Resource Allocation Framework for Multi-Layer Virtual Networks based on SDN

Thanh Nguyen Huu, Anh-Vu Vu, Dipl.; Cong-Duc Duong, Dipl.; Duc-Lam Nguyen, Dipl.; Manh-Nam Tran, M.Sc.; Quynh-Thu Ngo, Dr.; Tai-Hung Nguyen, Dr.; Thomas Magedanz, Prof. Dr.
An OpenFlow protocol to control traffic in network

Hubungi Duc D. mengenai pekerjaan anda

Log masuk untuk membincangkan sebarang butiran melalui sembang.

Pengesahan

Pekerja Bebas Pilihan
Identiti Disahkan
Pembayaran Disahkan
Telefon Disahkan
E-mel Disahkan
Facebook Dihubungkan

Pensijilan

us_eng_1.png US English 1 83%

Kemahiran Teratas

Verilog / VHDL 105 FPGA 74 Electronics 60 Technical Writing 43 Embedded Software 38

Layari Pekerja Bebas Serupa

Verilog / VHDL Designers in Vietnam
Verilog / VHDL Designers
Field-Programmable Gate Array Experts
Electronics Engineers

Layari Pameran Serupa

Verilog / VHDL
FPGA
Electronics
Technical Writing
Pengguna Sebelumnya
Pengguna Seterusnya
Jemputan berjaya dihantar!
Pengguna Berdaftar Jumlah Pekerjaan Disiarkan
Freelancer ® is a registered Trademark of Freelancer Technology Pty Limited (ACN 142 189 759)
Copyright © 2023 Freelancer Technology Pty Limited (ACN 142 189 759)
Memuatkan pratonton
Kebenaran diberikan untuk Geolocation.
Sesi log masuk anda telah luput dan telah dilog keluar. Sila log masuk sekali lagi.