Imej profil sonevw
@sonevw
Ahli semenjak 18 Oktober 2004
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sonevw

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## BIO **Education:** **1997 - 2002 : Electronics and Telecommunication Faculty, Polytechnic University, Bucharest, Romania, Department of Microelectronics.** **Diploma Title: eVC (verification component) for the I2C bus controller using "e" Specman.( passed with 10 on a 1-10 scale).** **Average Grade (on a 1-10 scale): First year : 8.60 ; Second year : 8.80, Third year : 9.30; Forth year : 9.20; Fifth year : 9.17. Average total :9.00** ## Area of Expertise **Area of expertise :** **EDA**: Verilog, "e" Specman, ModelSim, VCS, Medici , T-Suprem **Software**: C++, C#, Assembler, Perl, MatLab, Labview **Utilities**: Windows, Linux, Visio **Network** **protocols** : TCP/IP, SPI, USB, I2C, CAN **Projects : ** ****Design Engineer :**** ***Projects Fulfilled: *1) I have designed the slave module for an I2C bus controller using Verilog. The project was supposed to output the Verilog files for a complete I2C slave chip. This was a personal project and lasted for about 1 month. 2) I have been involved in the design of a CAN bus controller in a team of 5 engineers, using Verilog. My task was to design the main control module that I have finished in two months time. My module was designed to control the data flow inside the controller and also to handle the errors and to stop/suspend the entire controller. The output of the project was a set of HDL files of the design of CAN bus controller (approximately 12 000 logic gates). 3) I have been involved in the design of a USB 2.0 bus controller using Verilog in a team of 10 engineers. My task was to design the device state machine and an elastic buffer. I was involved in this project for two months. I wasn’t involved in this project until it’s end due to my assignation to the verification team to another project. The device state machine which I designed was responsible for the management of data flow inside the bus controller and the control of the peripheral devices (via USB ports). **Verification Engineer**** ***Projects Fulfilled: *1) I have participated in a training for Verisity "e" Specman Elite for one week, that has exposed to me to a new verification language, an object&aspect oriented language with a powerful random generator engine. The language is similar with C++ and JAVA but is oriented on hardware testing the main difference being the "real time" simulation property and the aspect oriented technology. 2) I was involved in the software verification of a FPGA translator between two protocols, leading the verification team of 3 engineers. The verification was done using the "e" and HDL simulator used was VCS. During this project I had 2 jobs to do. One was to coordinate the verification process of the protocol bridge and another one was to develop and to implement the test plan for transmission side of the bridge. The project lasted about 5 months. 3) I was involved in the software verification of a network processor. The verification was done using "e" language and HDL simulator was VCS. This was a demo project to show the advantages of "e" language versus other software verification tools like RuleBase and Verilog Plus. 4) I was involved in the development of a panel video card link model using "e" language in a team of 5 engineers. The HDL simulator is ModelSim. The model had to read data from image files (tiff files) recognize the encoding protocol (from a list of 10 possible protocols : RBC12, RBC24, YCbCr24, YC\_24, YCMuxed12, YCbCr444DVO, YC422DVO, YC656\_24, YC656\_12, YC656DVO\_12) and sent them to the bus. The receiver part of the module had to recognize the incoming data protocol, and convert them to a new protocol (from the 10 possible formats) and finally write the data to an output image file(tiff file). My part in this project was to develop the receiver side of the model (the one involved in the recognition and formatting of the input data to the proper protocol). The project lasted for about 6 months and was consider an outstanding success (the model was used in the verification of a video panel link and provided a bug free chip design) 5) I was involved in the software verification of a storage processor using "e" Specman Elite being part of a 12 engineers team. I was involved in this project for 6 months and my job was to develop/implement a validation plan for a module inside a network storage processor which had to update internal register of the processor and to arbiter several communication interfaces in order to deliver data to the TCP/IP block. 6) I was involved in a project with the Texas Instruments, France Division.   7) Currently in the Electronic Brake System industry working as a developing engineer in ABS, ESP and TCS Systems.**
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  • Imej Cody K. need simple C code commented $12.00 USD

    “Sone was very easy to work with. Co-operated with me and my needs extremely well. Even inquired on a particular variable to verify we were referencing the same thing. He wanted the project finished right and made sure that it was. VERY VERY RELIABLE. He said it would be done by friday and I got my finished project from him Thursday.. completed the project early and delivered without being pushy. A nice addition to the [login to view URL] family.”

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