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    5 verilog ascii tugasan ditemui, harga dalam USD
    Point Cloud Post Processor 4 days left
    DISAHKAN

    Require a post processor to take Velodyne LiDAR point cloud data (PCAP format) in the scanners coo...format) in the scanners coordinate system (SOCS) and convert to real world coordinates provided from a SBet (Smoothed Best Estimate of Trajectory) from the GPS/INS system (ASCII text). The data would be output in LAS format. Both files are time tagged.

    $1197 (Avg Bid)
    $1197 Avg Bida
    9 bida
    Discourse Plugin Update 4 days left
    DISAHKAN

    ...pull && /pups/bin/pups --stdin Already up-to-date. I, [2018-09-23T06:07:01.258185 #14] INFO – : Loading --stdin /pups/lib/pups/[login to view URL]:in split': invalid byte sequence in US-ASCII (ArgumentError) from /pups/lib/pups/[login to view URL]:inrun’ from /pups/bin/pups:8:in `’ 7bfaa7cccfa02ecadea2fc89e6ee2d54c5f813f8070f57d1babe4e40c688dee8 ** FAILED T...

    $37 (Avg Bid)
    $37 Avg Bida
    4 bida

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $182 (Avg Bid)
    $182 Avg Bida
    9 bida

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $146 (Avg Bid)
    $146 Avg Bida
    2 bida

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $415 (Avg Bid)
    $415 Avg Bida
    2 bida