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Arabic Translator
ASIC
Bash Scripting
Electrical Engineering
Very-large-scale integration (VLSI)
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$30 USD / jam
Bendera EGYPT
mansoura, egypt
$30 USD / jam
Sekarang jam 1:37 PTG di sini
Menyertai Jun 5, 2018
0 Syor

Mohamed Fathy R.

@MoRehan

 5.0 (15 ulasan)
5.6
5.6
100%
100%
$30 USD / jam
Bendera EGYPT
mansoura, egypt
$30 USD / jam
100%
Pekerjaan Disiapkan
68%
Mengikut Bajet
85%
Tepat Pada Masa
5%
Kadar Upah Semula

Digital IC Design Engineer - VLSI

Experienced Digital IC Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Synopsys Tools, Scripting languages and Linux. Highly motivated professional with a Bachelor's degree focused in Electronics & Communication Engineering from Mansoura University. Eager to learn and develop new skills.
Freelancer Electrical Engineers Egypt
Lihat semua Electrical Engineers dalam Egypt

Hubungi Mohamed Fathy R. tentang pekerjaan anda

Log masuk untuk membincangkan sebarang butiran melalui sembang.

Portfolio

5134537
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
5134512
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
5134537
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
Hardware implementation for BCC encoder based on IEEE 802.11af standard. Binary Convolution Encoder usually found inside communication systems. It supports various data rates 2/3, 3/4 and 5/6 which is generated from the mother rate 1/2.
ASIC Implementation of BCC Encoder with Multi Rate operation
5134512
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm
Hardware implementation for Binary Convolutional Codes Decoder (BCC), based on the Viterbi algorithm. also, this core support multi-rate operation based on code puncturing.
ASIC Implementation of BCC Decoder - Viterbi algorithm

Ulasan

Perubahan disimpan
Menunjukkan 1 - 5 daripada 15 ulasan
 Tapis ulasan mengikut:
5.0
$600.00 USD
VLSI Project
رائع جدا جدا ، وتسليم بالموعد المناسب
Electrical Engineering
Arabic Translator
Very-large-scale integration (VLSI)
Bash Scripting
+1 lagi
B
Closed User
@Btm1111
•
5 bulan yang lalu
5.0
$590.00 USD
VLSI project - Full flow
شاكر لك استاذ ريحان على حسن التعامل
Electrical Engineering
Arabic Translator
Very-large-scale integration (VLSI)
Bash Scripting
+1 lagi
S
Closed User
@sulltan0707
•
11 bulan yang lalu
5.0
$600.00 USD
Project for Mohamed Fathy R.
He is a good eng and
Electrical Engineering
Arabic Translator
Very-large-scale integration (VLSI)
Bash Scripting
+1 lagi
H
Closed User
@Hxr78hxr
•
2 tahun yang lalu
5.0
$300.00 USD
Project for Mohamed Fathy R.
الصمت في حرم الجمال جمال رجل متمكن ما شاء الله في المشروع يعطيه ألف عافية و كذلك دقيق في تسليم المشروع بالوقت
Electrical Engineering
Arabic Translator
Very-large-scale integration (VLSI)
Bash Scripting
+1 lagi
I
Closed User
@ibrahim0550
•
2 tahun yang lalu
5.0
$300.00 USD
Project for Mohamed Fathy R. -- 2
Well done , I will be working with him again .
Electrical Engineering
Arabic Translator
Very-large-scale integration (VLSI)
Bash Scripting
+1 lagi
A
Closed User
@Abdulmajeed121
•
2 tahun yang lalu

Pengalaman

Digital IC Design Engineer

Si-Vision
Feb 2020 - Hari ini
Si-Vision is the biggest VLSI design centre in Egypt which lead the market nowadays. I work as a full-time Digital IC Design Engineer. and I'm responsible for designing mature HDL and testing it. Scripting is a key player in my day to day activity. so I'm confident with python, bash scripting and other types of scripting languages.

Pendidikan

Bachelor's of Science degree in Electronics and Communication Engineering

Mansoura University, Egypt 2014 - 2019
(5 tahun)

Hubungi Mohamed Fathy R. tentang pekerjaan anda

Log masuk untuk membincangkan sebarang butiran melalui sembang.

Pengesahan

Pekerja Bebas Pilihan
Identiti Disahkan
Pembayaran Disahkan
Telefon Disahkan
E-mel Disahkan
Facebook Dihubungkan

Kemahiran Teratas

Electrical Engineering 19
Arabic Translator 18
Very-large-scale integration (VLSI) 18
Bash Scripting 18
ASIC 18

Layari Pekerja Bebas Serupa

Electrical Engineers in Egypt
Electrical Engineers
Arabic Translators
VLSI Engineers

Layari Pameran Serupa

Electrical Engineering
Arabic Translator
Very-large-scale integration (VLSI)
Bash Scripting
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