Rudy B. Profile

0.0

(0 ulasan)

Anda kini mengikuti

Ralat mengikuti pengguna.

Pengguna ini tidak membenarkan pengguna untuk mengikuti mereka.

Anda telah mengikuti pengguna ini.

Pelan keahlian anda hanya membenarkan 0 mengikuti. Naik taraf di sini.

Berjaya menyahikut

Ralat tidak mengikuti pengguna.

Anda berjaya mengesyorkan

Ralat mengesyorkan pengguna.

Sesuatu telah berlaku. Sila segar semula halaman dan cuba lagi.

E-mel berjaya disahkan.

redondo beach,

united states

Sekarang jam 12:51 PTG di sini

Menyertai September 19, 2012

0 Cadangan

Rudy B.

@rudy03

0.0

(0 ulasan)

0.0

redondo beach,

united states

N/A

Pekerjaan Disiapkan

N/A

Mengikut Bajet

N/A

Tepat Pada Masa

N/A

Kadar Upah Semula

FPGA Designer

Over 7 years of experience in various types of algorithm developments, vhdl/verilog design, embedded processing. Design includes various high speed video applications, and heavily involved in signal processing and communication systems with dense DSP application such as FFT, channelizer, modulator/demodulator and various filter designs. Also involved in embedded processors using Microblaze/PowerPc, and developing APIs using C/C++.

Lihat semua C Programmers dalam United States

Hubungi Rudy B. tentang pekerjaan anda

Log masuk untuk membincangkan sebarang butiran melalui sembang.

Portfolio

272429

vhdl snippet

272429

vhdl snippet

Ulasan

Perubahan disimpan

Tiada ulasan untuk dilihat di sini!

Pengalaman

Startup Company

Apr 2010 - Hari ini

Working on Video Compression algorithm development. Developed full rate HD vdieo system, capturing over firewire interface. applying compression methods, and transfer the data over gigabit interface to another board. Developed all the necessary interfaces and the .NET API.

Northrop Grumman Aerospace System

Apr 2006 - Mei 2010 (4 tahun, 1 bulan)

Beamformer Algorithm design. Adaptive LMS filter design. Fixed-point Wideband Subchannelizers design, including presume window, DFT engines, filter banks, and barrel shifters. Advanced FPGA designing, packing and optimization of the specific targeted FPGA device. back-end processes from syntheses to place & route. Performed thorough floor-planning and advanced placement, using planAhead/FPGA-Editor for timing closure on highly utilized FPGAs. Developed bit-to-bit accurate models, in C/C++ Used Ma