Yana T. Profile

5.0

(4 ulasan)

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E-mel berjaya disahkan.

$20 USD / jam

pontianak,

indonesia

$20 USD / jam

Sekarang jam 2:03 PTG di sini

Menyertai Mei 20, 2015

0 Cadangan

Yana T.

@yanatejaip5s

5.0

(4 ulasan)

3.2

100%

$20 USD / jam

pontianak,

indonesia

$20 USD / jam

100%

Pekerjaan Disiapkan

100%

Mengikut Bajet

100%

Tepat Pada Masa

N/A

Kadar Upah Semula

RTL Design Engineer

An RTL Design Engineer with extensive experience in both Front-end and Back-end Digital IC Design. I possess a strong and comprehensive understanding of Microelectronics, particularly in the field of Digital IC Design. I have worked on building various components of Digital Baseband Processors. My expertise includes proficient use of Verilog, TCL Scripting, C/C++ Programming, MATLAB, ModelSim, Xilinx Vivado, Mentor Graphics (Pyxis), Synopsys (VCS, Astro, PrimeTime), and Cadence (Virtuoso, Genus, Xcelium)

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Portfolio

Synopsys Astro is the Automatic Place and Route (PnR) tool from Synopsys. It takes synthesized gate-level netlist and a standard cell library as input, then produces layout as an output. Synopsys Astro can also perform verification and generate back-annotation scripts. Besides that it is for Clock Tree Synthesis(CTS), PnR, Design For Manufacturing (DFM), Design Rule Check (DRC) and Layout Vs Schematic (LVS)

Back End Implementation of Basic Arithmetic Operation CNN

This CNN architecture give an instruction in the final output using maximum value detection as an activation function whether the input is horizontal or vertical with image classification using edge detection. The architecture can detect image classification input whether it vertical or horizontal and do the control. If it detect vertical so it will do indata1 + indata2 and if it detect horizontal it will do the indata1 x indata2. This architecture need bigger area but it can run in high speed and produce high throughput, there is no hold time negative slack and setup time negative slack as well

Basic Arithmetic Operation Controller with CNN

The Aim of this design is to ensure that the CMFB will give feedback or response to the Folded Cascode Amplifier to do some correction of DC output for the output of amplifier. According to the reference on the lecture, the output of the Folded Cascode Amplifier will be half of the vdd or Vref = Vdd/2. The results shows that it bring the output to the half of Vdd for about 900 mV, it have a 41.98 dB DC gain and then it can be say that the circuit is stable because having positive 79.39° phase margin

Design of a Folded Cascode with Common Mode Feedback (CMFB)

This project presents a voltage controller oscillator with CMOS transistor. The output of this circuit will be oscillate due to control of a voltage. The CMOS VCO will be run in the target frequency of 2.6GHz for the output voltage, have a low power consumption due to the low current of the drain it’s about ≤ 6.3mA in the drain CMOS current and have an enough large output power for about more than 4dbm

Design of Circuit CMOS VCO with 180nm Technology

This exploration project seeks to renew and make new innovations for the realization of applied craft work in Indonesia by combining textile craft science with exploration techniques that focus on the stylization of archipelago ornaments, laser cut techniques, several surface textile exploration techniques as well as electronic scientific exploration, namely a series of LEDs circuits

Exploration of Central Java Cultural Motives in Interior Pro

The system created is an angular velocity measuring device from a rotating motor with an infrared sensor. The output of sensor is used as input by utilizing the ADC inside the microcontroller and convert it to the speed. The speed measurement will be displayed on the LCD and it also displayed in the smartphone with wireless communication utilizing Wi-Fi baseband

Non Contact of Angular Speed Measurement Device

Back End Implementation of Basic Arithmetic Operation CNN

Basic Arithmetic Operation Controller with CNN

Design of a Folded Cascode with Common Mode Feedback (CMFB)

Design of Circuit CMOS VCO with 180nm Technology

Exploration of Central Java Cultural Motives in Interior Pro

Non Contact of Angular Speed Measurement Device

Ulasan

Perubahan disimpan

Menunjukkan 1 - 4 daripada 4 ulasan

Tapis ulasan mengikut:

5.0

₹6,500.00 INR

Rtl implement

Good guy Good guy Good guy

Electronics

Verilog / VHDL

Microcontroller

Electrical Engineering

FPGA

Ajeet K.

@ajeetstudent6

•

2 bulan yang lalu

5.0

€195.00 EUR

Project for Yana T.

Good communication, he did a great work eventhough im asking so much but he still can made it right. Even give me some suggestions for my project documentation.

C Programming

Electronics

Electrical Engineering

Arduino

+1 lagi

Tasya A.

@tasyaarie

•

3 tahun yang lalu

5.0

$55.00 USD

Project for Yana T.

Great work, will hire him again.

C Programming

Electronics

Electrical Engineering

Arduino

+1 lagi

Closed User

@aleksandrbraus

•

3 tahun yang lalu

5.0

$45.00 USD

CRC-7 FPGA Verilog Implementation

The work is done before the deadline. Communication and understanding of the issue is present. I would love to hire Yana again!

C Programming

Verilog / VHDL

Microcontroller

Electrical Engineering

FPGA

Closed User

@zobovov

•

3 tahun yang lalu

Pengalaman

Mälardalen University

Feb 2023 - Hari ini

- Debugged and executed PipeCNN, an OpenCL-based accelerator for Large-Scale Convolutional Neural Networks (CNNs) such as LENET-5, VGG-16 and RESNET-50 on the Zynq UltraScale+ MPSoC ZCU104 FPGA board - Created inference MATLAB models using pre-trained Model Zoo for both LENET-5 and VGG-16 Convolutional Neural Networks (CNN) - Developed a fully RTL Maxpool Kernel using Verilog instead of provided HLS C++ code, and extensively verified its functionality using a direct testbench on Xilinx Vivado

Krakatoa Technologies

Jul 2022 - Feb 2023 (7 bulan, 1 hari)

- Perform Logic Synthesis with Cadence Genus using Low Power Techniques and Generate Optimized Gate Level Netlist for Timing, Area and Power - Perform Gate Level Netlist Simulation with Zero Delay Simulation, Unit Delay Simulation using Cadence Xcelium to Ensure Functionality Correctness Match to the RTL Behavioral Simulation - Perform Power Estimation and Analysis at RTL and Gate Level Netlist

Microelectronics Center ITB

Nov 2019 - Nov 2020 (1 tahun)

- Developing and Integration Existing IP Core using Xilinx IP Core as well as 3rd Party IP on Vivado to Build a Digital Baseband Processor - Build Direct Test Testbench for Simulation and Verification with Xilinx Vivado and Compared Each IP Core Output Based on Reference Model in MATLAB to Ensure the Functionality - Developing and Testing Linux Kernel of MAC Layer with C Programming to push data into PHY Layer