bubble level project

Ditutup Disiarkan 6 tahun lepas Dibayar semasa penghantaran
Ditutup Dibayar semasa penghantaran

the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board.

In the video attached in the .zip, the operation of the project

FPGA Verilog / VHDL

ID Projek: #15762690

Tentang projek

5 cadangan Projek jarak jauh Aktif 6 tahun lepas

5 pekerja bebas membida secara purata $74 untuk pekerjaan ini

sourindu

A proposal has not yet been provided

$55 USD dalam 4 hari
(1 Ulasan)
2.3
alexstyle

The offer is purely indicative and we could discuss the details by chat.

$35 USD dalam 10 hari
(0 Ulasan)
0.0
chinhtranduc

I have experience working on FPGA kits such as Xilinx Artix 7 development board, Numato NESO,.. Relevant Skills and Experience FPGA, Verilog/VHDL, image processing, C/C++ Proposed Milestones $35 USD - please add more Lagi

$35 USD dalam sehari
(0 Ulasan)
0.0