1. Parallel coding with configurable parallelism 2. Parallel decoding with configurable parallelism 3. Decoding and error correction can be carried out at the same time 4. Find the wrong position in parallel, and the parallelism can be configured 5. The data block size can be 512B / 1024B 6. Support error correction bits 24， 32 and 40 under block size of 1024B
Need a physicist as second reviewer of a project system involving fpga configuration. Please specify your experience in fpga based projects and physics firstly in your bid. More details to competent bidders.
I am looking for a verilog developer to help build a chip test bench on Modelsim. Its a short project and should take 3-4 hours
i need someone that can do 3d character animation for me s sample and deliver in 4k and later get discuss on the video budget and timeframe but i can only order if you are able to do the character as sample first,And after that the video will be episode by episode,Thanks.
Project is for fpga chip vu35p. Algorithm beam hash 3. Must work via uart and have a windows miner exe file to launch the miners once programmed . Looking for 250 sol hashrate or higher . 2 week build timeline. The vu35p has 8gb hbm on chip memory which should make this a simpler project