Verilog / VHDL Jobs

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Tentang Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Upah Verilog / VHDL Designers

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    Microprocessor systems help 6 hari left

    you are required to create your own device. You are allowed to chose your own topic, however, it should meet the minimum requirements listed below. There will be points distributed for creativity, keep that in mind. Your setup should feature microcontroller to microcontroller communication. Additionally you must use at least 3 of the following systems: Matrix based input Matrix based output Tim...

    Kejuruteraan Elektrik Elektronik Mikropengawal Verilog / VHDL Tanpa Wayar
    $40 (Avg Bid)
    $40 Avg Bida
    4 bida
    Bida sekarang
    Design a counter using Quartus II ( VHDL ) 6 hari left

    Design a counter for the KL shopping mall entrances to allow maximum 99 shoppers at a time to promote social distancing. [Hints: Reset button can be used to clear the counter every morning; in/out signal can be used to control the up/down counter while people are moving in and out; red-light can be used to indicate whether they are allowed to enter] The report should include the following : -...

    Altera Quartus Reka Bentuk Digital Verilog / VHDL
    $30 (Avg Bid)
    $30 Avg Bida
    1 bida
    Bida sekarang
    Parsing Infix notation to ONP - Verilog [FGPA] 6 hari left

    Parsing Infix notation to ONP i Verilog [FGPA] and calculating the value in two modules

    FPGA Verilog / VHDL
    $40 (Avg Bid)
    $40 Avg Bida
    1 bida
    Bida sekarang
    Xilinx FPGA Expert 5 hari left
    DISAHKAN

    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

    Pengaturcaraan C Kejuruteraan Elektrik Elektronik Mikropengawal Verilog / VHDL
    $562 (Avg Bid)
    $562 Avg Bida
    4 bida
    Bida sekarang
    Seo para smartivhd.com 4 hari left

    oi, preciso de seo para [log masuk untuk melihat URL], quero a melhor classificação no [log masuk untuk melihat URL] globalmente, qualquer um pode me dar bons resultados palavras-chave, melhor provedor de iptv nos EUA, melhor provedor de iptv no Canadá, melhor provedor de iptv em u

    Pemasaran Internet SEO SEO Auditing Verilog / VHDL
    $257 (Avg Bid)
    $257 Avg Bida
    39 bida
    Bida sekarang
    Rewrite C code to make it synthesizable to simulate in HLS tool - Tongue Segmentation 4 hari left
    DISAHKAN

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    Pengaturcaraan C JavaScript PHP Verilog / VHDL
    $170 (Avg Bid)
    $170 Avg Bida
    2 bida
    Bida sekarang
    One Simulator Expert 4 hari left
    DISAHKAN

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    Pengaturcaraan C Certified Information Systems Security Professional (CISSP) Cisco Pentadbiran Rangkaian Verilog / VHDL
    $215 (Avg Bid)
    $215 Avg Bida
    3 bida
    Bida sekarang
    HLS Tools VHDL Expert C Programmer 4 hari left
    DISAHKAN

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    Pengaturcaraan C Elektronik Verilog / VHDL
    $155 (Avg Bid)
    $155 Avg Bida
    4 bida
    Bida sekarang
    Write C code to make it synthesizable to simulate in HLS tool - Tongue Segmentation 4 hari left
    DISAHKAN

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    Pengaturcaraan C Kejuruteraan Elektrik Kejuruteraan Perisian Verilog / VHDL
    $140 (Avg Bid)
    $140 Avg Bida
    4 bida
    Bida sekarang
    electronical eng very small project (signal) 4 hari left
    DISAHKAN

    I need help person who know this subject -Signal Exponential sin and cos unit step dirac Delta Shifting and scaling of signal -systems linarity LTI system convolution -furier transforms -modulation teory

    Kejuruteraan Elektrik Elektronik Matlab and Mathematica Signal Processing Verilog / VHDL
    $18 / hr (Avg Bid)
    $18 / hr Avg Bida
    8 bida
    Bida sekarang
    Rewrite C code to make it synthesizable to simulate in HLS tool - Tongue Segmentation 4 hari left
    DISAHKAN

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    Pengaturcaraan C JavaScript PHP Verilog / VHDL
    $156 (Avg Bid)
    $156 Avg Bida
    6 bida
    Bida sekarang
    One Simulator Expert 4 hari left
    DISAHKAN

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    Certified Information Systems Security Professional (CISSP) Cisco Kejuruteraan Pentadbiran Rangkaian Verilog / VHDL
    $140 (Avg Bid)
    $140 Avg Bida
    1 bida
    Bida sekarang
    design OPAMP integrator using two stage CMOS amplifier in cadence Virtuoso tool 4 hari left

    Duration 1 week, expected cost 7k

    Reka Bentuk Litar Kejuruteraan Elektrik Elektronik Kejuruteraan Verilog / VHDL
    $8 - $21
    $8 - $21
    0 bida
    Bida sekarang
    adaptive cruise control using arduino on simulink 4 hari left

    Adaptive Cruise Control Objective Use Simulink environment to develop and implement an adaptive cruise control system for vehicles that automatically adjusts the vehicle speed to maintain a safe distance from vehicles ahead. Hardware Arduino uno x 1, button x 5, distance sensor x 1, 4 digit 7-segment anode display x 1 Description Implement an adaptive cruise control system with five buttons of (1...

    Arduino Kejuruteraan Elektrik Elektronik Mikropengawal Verilog / VHDL
    $99 (Avg Bid)
    $99 Avg Bida
    5 bida
    Bida sekarang
    an expert on verilog, QUARTUS and MODELSIM 4 hari left
    DISAHKAN

    I need someone who knows verilog hdml, quartus and modelsim.

    Altera Quartus Reka Bentuk Digital Digital Electronics Kejuruteraan Elektrik Verilog / VHDL
    $21 (Avg Bid)
    $21 Avg Bida
    8 bida
    Bida sekarang
    My project 4 hari left

    Hi I need an expert for the optimization of PSO. This system is an inverted pendulum system that uses Sliding Mode Control (SMC) to stabilize the inverted pendulum output. And as an addition, I want to use the Particle Swarm Optimization to get the best 'lamda' value which is the sliding surface coefficient, thus, optimizing the output. The SMC controller and the inverted pendulum system...

    Kejuruteraan Elektrik Elektronik Kejuruteraan Matlab and Mathematica Verilog / VHDL
    min $50 / hr
    min $50 / hr
    0 bida
    Bida sekarang
    Xilinx FPGA coding 3 hari left
    DISAHKAN

    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

    Arduino Pengaturcaraan C Elektronik Mikropengawal Verilog / VHDL
    $644 (Avg Bid)
    $644 Avg Bida
    8 bida
    Bida sekarang
    Digital signal processing 2 hari left

    need a DSP teacher for a project

    Digital Signal Processing Kejuruteraan Elektrik Elektronik Matlab and Mathematica Verilog / VHDL
    $14 (Avg Bid)
    $14 Avg Bida
    4 bida
    Bida sekarang
    circuit design and coding -- 2 2 hari left
    DISAHKAN

    I have a project about circuit design + coding + teaching me how to do it hardware and telling me the components it is about current leakage detector. need to finish the design and coding by today. my budget is 30-60$

    Reka Bentuk Litar Kejuruteraan Elektrik Elektronik Kejuruteraan Verilog / VHDL
    $58 (Avg Bid)
    $58 Avg Bida
    7 bida
    Bida sekarang
    Clock recovery model 2 hari left
    DISAHKAN

    Debugging a clock recovery model in verilog

    Reka Bentuk Litar FPGA Kejuruteraan Telekomunikasi Verilog / VHDL Tanpa Wayar
    $21 (Avg Bid)
    $21 Avg Bida
    3 bida
    Bida sekarang
    PLC Programmer 1 hari left

    We are looking for a PLC programmer to develop a new programing ladder for operation of our seamwelding unit using Siemens of Allen Bradly units. The program will involve programing operation of approximately analog/digital I/Os.

    Kejuruteraan Elektrik Elektronik Mikropengawal PLC & SCADA Verilog / VHDL
    $1080 (Avg Bid)
    $1080 Avg Bida
    44 bida
    Bida sekarang
    Tiny odification on a verilog model 1 hari left
    DISAHKAN

    Do NOT big if you don't have the knowledge. This task is simple but it needs some background so you don't have to spend too much time to think about it if you have the strong knowledge ok! I have a model for a clock recovery including encoder/decoder with the emphasis to the decoder, the decoder needs to estimate the clock from the data, the model already does this job but I need to add ...

    Reka Bentuk Litar Kejuruteraan Elektrik FPGA Verilog / VHDL Wireless Radio Frequency Engineering
    $18 (Avg Bid)
    $18 Avg Bida
    6 bida
    Bida sekarang
    logic design expert for me 1 hari left
    DISAHKAN

    must be extremely expert in : CMOS transistor networks Noise Margins Analysis of Sequential Circuit, State Diagram, Dead states, Synchronizers Synthesis of Sequential Circuit, Min Length and One-Hot encoding Synthesis, Mealy vs Moore Combinational Loops, State minimization The D Flip-Flop, shift registers, KMAPS/ SOP/ POS Transmission Gates (4-8 problems)

    Reka Bentuk Litar Kejuruteraan Elektrik Kejuruteraan Kejuruteraan Perisian Verilog / VHDL
    $121 (Avg Bid)
    $121 Avg Bida
    10 bida
    Bida sekarang
    I want to appoint a mips programmer to solve two question for me in 2 hours 1 hari left

    The question will be basic question like using function call, loop etc type to solve any polynomial equation or print string etc

    Himpunan Pengaturcaraan C Kejuruteraan Verilog / VHDL Penghimpun x86/x64
    $1 / hr (Avg Bid)
    $1 / hr Avg Bida
    1 bida
    Bida sekarang
    logic design expert new 1 hari left
    DISAHKAN

    must be extremely expert in : CMOS transistor networks Noise Margins Analysis of Sequential Circuit, State Diagram, Dead states, Synchronizers Synthesis of Sequential Circuit, Min Length and One-Hot encoding Synthesis, Mealy vs Moore Combinational Loops, State minimization The D Flip-Flop, shift registers, KMAPS/ SOP/ POS Transmission Gates (4-8 problems)

    Reka Bentuk Litar Kejuruteraan Elektrik Kejuruteraan Kejuruteraan Perisian Verilog / VHDL
    $101 (Avg Bid)
    $101 Avg Bida
    6 bida
    Bida sekarang
    Verilog coding 4 jam left

    write a verilog code from RAM using icaurus verilog

    Himpunan Kejuruteraan FPGA Verilog / VHDL Very-large-scale integration (VLSI)
    $7 / hr (Avg Bid)
    $7 / hr Avg Bida
    5 bida
    Bida sekarang
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