Hi,
Client want help in VHDL homework. It will not be complicated for expert. I will share more info with right candidate. I want to start job asap. We want to use ModalSim.
Note: Bid only if you have experience with VHDL. I am expecting job done within $50. And, you can start today.
Thanks
Hi,
Thanks for the project.
I have found out what might be the error and why the output has not been shown...
I want to demonstrate it by today...
Regards,
Gopi
Hi Dear,
I'm a Verification engineer working for STMicroelectronics in Grenoble France. I have a strong experience in Design and Verification using VHDL/Verilog.
Have you please give some details concerning your project?
Best regards,
Mehdi
Hi,
I would be happy to help you, I have a master degree in electronics and computer science engineering. I have been programming in VHDL for many years.
In my workstation I have modelsim installed.
Message me so we can talk about these homework.
Cheers
Hi,
I am FPGA expert and familiar in VHDL/verilog/AHDL/ABEL. i have huge experience in all FPGA platform and I have done project like Unmanned aircraft design for deffence and many projects in medical domain. I can do any kind of FPGA/CPLD work.