Design and implementation of MPEG-2 encoder on Altera FPGA -- 2

$350-850 USD

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$350-850 USD

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Design an MPEG-2 encoder IP Core in Verilog to compress a video signal resolution 640x480 and should have the performance to make video streaming. The input images will be in the RGB color space. The IP core arquitecture should be Pipeline. The output bitstream resulting should be compatible with a MPEG2 reproductor for testing.

C Programming

FPGA

Verilog / VHDL

ID Projek: 10097940

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@achievemani

Cumulative experience of 30 years experienced VLSI professionals, Would like to work in exciting projects like this.

$388 USD dalam 7 hari

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6 pekerja bebas membida secara purata $623 USD untuk pekerjaan ini

@rohi1710rohi1710

I have worked as FPGA engineer for 6 years and out of which I have worked in video and image processing domain for 5 years. I have expertise in verilog and VHDL both. I can complete this job with greater efficiency.

$722 USD dalam 13 hari