I'm working on FPGAs and hdl programming 3 years ago, machine states, architectural programming and many other advanced features. I've made many project on SoC devices (Cyclone V, Arria 10) like SPI protocole, CORDIC algorithm for computing sinus and cosinus functions, H bridge controller using hps and fpga resources. This summer I also worked with CERN on a very interesting project, it was the implementation of partial reconfiguration feature on the Arria 10 GX device, it was over two interfaces, first over JTAG and then upgraded to the PCIe. the design work well, as we implement logic to communicate with the board over the system host, if you're interested in these skills, please feel free to contact me at any time.