Computer Science—Verilog, VHDL

$10-30 USD

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sekitar 10 tahun yang lalu

$10-30 USD

Dibayar semasa penghantaran

1- to write verilog code 2- to write a test bench code 3- compile both 4- simulate using (sim vision) 5-synthesize 6- testing waveforms

Verilog / VHDL

ID Projek: 5833398

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Dianugerahkan kepada:

@noumiawan1991

I can do your project within two days. that way you will still be ask for modifications if the task doesn't meet your standard before your project deadline

$55 USD dalam 2 hari

5.0

(2 ulasan)

3.3

8 pekerja bebas membida secara purata $56 USD untuk pekerjaan ini

@JSTechSol

A proposal has not yet been provided

$35 USD dalam 1 hari

5.0

(3 ulasan)

3.8

@zarnescugeorge

Hello! I can help you right away! I have 8 years experience writing vhdl for fpgas! I can help you with your project but with vhdl

$138 USD dalam 1 hari

4.9

(5 ulasan)

3.5

@kaveirious

Hi, I want to undertake your interesting project. I am a professional Verilog HDL (and VHDL) developer with 15+ years of experience. I have implemented and delivered quite a few projects, such as processor designs, custom controllers, FFTs and signal processing projects and so on. I understand that you want both designs (the BCD-to-excess3 and register file) implemented as part of the project. Quality work guaranteed, I will also include self-checking testbenches that run automatic diagnostics for simulation pass/fail. Of course you can always inspect waveform data and will provide the writeup as requested in the assignments' descriptions.

$100 USD dalam 3 hari