verilog ALU with test bench

I have to write the Verilog code(will post what i came up with below) for a 4-bit arithmetic/logic unit (ALU). The requirements are as follows: The ALU operate on inputs that are 4 bits wide. inputs aluin_a and aluin_b, a carry in named Cin and operation code named OPCODE. Inputs aluin_a, aluin_b and OPCODE are 4 bits wide. Cin is 1-bit wide. outputs will be alu_out and Cout. Output alu_out (which is the result of the ALU operation) is 4 bits wide. Cout is the carry out and will be 1 bit. A 1-bit flag will be set on overflow (named OF), assume this is the overflow for numbers which have sign. A test bench should be created to thoroughly test the ALU. Inside the top-level, you should instantiate a 4-bit ripple adder which in turn instantiates a 1-bit full adder. Inputs to the 4-bit adder can be chosen based on OPCODES using a case statement. 4-bit subtraction can be implemented by taking the 2’s complement of aluin_b prior to presenting it as an input to the adder module. Boolean expressions may be used for logical operations *NOP – No Operation Note you must interpret these operations based on Verilog syntax and directions given in the specification. In addition, 1. Cout should be the carry out (1 bit) 2. If arithmetic overflow occurs signal OF should be set to 1, otherwise it should be 0, since this makes no sense for logic operations Cout and OF should be set to 0 for those. 3. You need a test bench named ALU_tb which should test all operations as well as, Cin, Cout, and OF under all operations. Note the Cout and OF should be 0 for non arithmetic operations. I have written the ALU, ripple adder, full adder, half adder and 2's compliment. I need someone to check it to make sure I have it completed correctly and if not please tell me where I went wrong and how to fix it. Also I need to write a test bench so I can test the ALU. // ALU module ALU(input [3:0] aluin_a, aluin_b, OPCODE, input Cin, output reg [3:0] alu_out, output reg Cout, output OF); reg [3:0] Bin; wire [3:0] Bn, S; wire Co; com2s C1(aluin_b, Bn); FA4 fa1(aluin_a, Bin, Cin, S, Co, OF); always @ (*) begin Bin = 4'b0000; alu_out = 4'b0000; Cout = 'b0; case (OPCODE) // add 4'b1000 : begin alu_out = aluin_a+aluin_b; end // add with Cin 4'b1001 : begin alu_out = aluin_a+aluin_b+Cin; end // sub a from b 4'b1010 : begin alu_out = aluin_a-aluin_b; end // bitwise NAND 4'b0000 : begin alu_out = ~(aluin_a & aluin_b); end // bitwise NOR 4'b0001 : begin alu_out = ~(aluin_a | aluin_b); end // bitwise XOR 4'b0010 : begin alu_out = aluin_a^aluin_b; end // bitwise inversion 4'b0100 : begin alu_out = ~aluin_a; end // logical left shift 4'b0101 : begin alu_out = aluin_a << 1; end default : begin alu_out = 0; Cout = 0; end endcase end endmodule //4 bit ripple adder module FA4(input [3:0] A, B, input Cin, output [3:0] Sum, output Cout, OF); wire Cout1, Cout2, Cout3; FA fa1 (A[0], B[0], Cin, Sum[0], Cout1); FA fa2 (A[1], B[1], Cout1, Sum[1], Cout2); FA fa3 (A[2], B[2], Cout2, Sum[2], Cout3); FA fa4 (A[3], B[3], Cout3, Sum[3], Cout); xor X1 (OF, Cout3, Cout); endmodule // 2's Compliment module com2s (input [3:0] B, output [3:0] Bn); wire [3:0] Bn1; wire OF; assign Bn1=~B; FA4 fa1 (Bn1, 4'b0000,1'b1,Bn,Cout,OF); endmodule // 1 bit full adder module FA(input A, B, Cin, output S, Cout); wire Sum1, Cout1, Cout2; HA ha1(A, B, Sum1, Cout1); HA ha2(Sum1, Cin, S, Cout2); or O1 (Cout, Cout1, Cout2); endmodule // 1 bit half adder module HA(input A, B, output Sum, Cout); assign Sum = A^B; assign Cout = A&B; endmodule