Read data sensor

Hi, I have worked on similar projects, would like to ask what kind of sensor you have? What is the datarate? Which FPGA are you targeting? Do you need processing of data on the fpga or would you like to transfer the data to a processor? We can discuss these and other design decisions. please drop a line on the chat window for any questions you might have. best regards,

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

A highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, VLSI/CMOS Design, Cadence ADE, /Virtuoso/Layout/Digital ASIC Design from RTL-GDSII. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other projects

Hi, Let me know the detail of your project. what kind of interface you use? What kind of Xilinx series you are using? and what kind of output you want ? Lets discuss it, Best Regards, Rijal

i have very Good command over FPGA Xillinx projects, recently i have done 2 projects related to this field, you can see on my profile. I am very confident that i can handle your work

This bid is to review the requirements and to make a first sketch implementation proposal based on the requirements. Later implementation, time-frame and cost has to be negotiated separately.

WOrking as a Design Engineer in Qualcomm Ind PVt ltd, this maybe my first proiject here, so im quoting you cheap. utilize it.

Hello, My graduation project was on FPGAs I have worked on professional FPGA, CPLD, processor and Electronics designs for a well reputed large company for about 7 years. Im running my own business now, I have helped Bachelor degree graduates on their FPGA projects before. The task you offered doesnt seem complicated for the skill I can offer. Please chat, hopefully I can help and get to know a future FPGA professional mate as well.

I am a professional FPGA Developer. I am working in FPGA industry for last 6 years. I have expertise over both Xilinx and Altera FPGA tools

I have 15 plus year experience in Fpga design with a PhD in fast communication protocols. Will be able to help explain the design as well. We can discuss details on the freelance messenger Relevant Skills and Experience VERILOG vhdl Dsp design Algorithms Matlab

Hi, I have 4 years of experience in develping fpga ip with xilinx tool flow. I have designed lots of standart serial interface like SPI, I2C etc.